Simulation Results

Simulation Results: kmac/unmasked

06/06/2026 15:22:54 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
95.76 %

code
92.22 %

assert
98.80 %

func
96.25 %

line
97.66 %

branch
95.95 %

cond
94.77 %

toggle
100.00 %

FSM
72.73 %

Validation stages

V1		100.00%
V2		95.50%
V2S		100.00%
V3		80.00%

35/35 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				20	20	100.00
	kmac_smoke	50.760s	3800.459us	20	20	100.00
csr_hw_reset				1	1	100.00
	kmac_csr_hw_reset	1.340s	95.193us	1	1	100.00
csr_rw				5	5	100.00
	kmac_csr_rw	1.540s	68.700us	5	5	100.00
csr_bit_bash				1	1	100.00
	kmac_csr_bit_bash	19.300s	1656.256us	1	1	100.00
csr_aliasing				1	1	100.00
	kmac_csr_aliasing	7.510s	137.796us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	kmac_csr_mem_rw_with_rand_reset	2.810s	81.738us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	kmac_csr_rw	1.540s	68.700us	5	5	100.00
	kmac_csr_aliasing	7.510s	137.796us	1	1	100.00
mem_walk				1	1	100.00
	kmac_mem_walk	1.070s	32.447us	1	1	100.00
mem_partial_access				1	1	100.00
	kmac_mem_partial_access	1.730s	18.502us	1	1	100.00

403/422 passed

95.50 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
long_msg_and_output				20	20	100.00
	kmac_long_msg_and_output	4690.570s	499841.298us	20	20	100.00
burst_write				20	20	100.00
	kmac_burst_write	908.650s	54042.001us	20	20	100.00
test_vectors				40	40	100.00
	kmac_test_vectors_sha3_224	2738.900s	531378.738us	5	5	100.00
	kmac_test_vectors_sha3_256	2570.470s	212325.920us	5	5	100.00
	kmac_test_vectors_sha3_384	1554.630s	261429.640us	5	5	100.00
	kmac_test_vectors_sha3_512	1019.360s	48834.719us	5	5	100.00
	kmac_test_vectors_shake_128	226.530s	58005.367us	5	5	100.00
	kmac_test_vectors_shake_256	2472.250s	365021.799us	5	5	100.00
	kmac_test_vectors_kmac	2.750s	381.294us	5	5	100.00
	kmac_test_vectors_kmac_xof	2.690s	38.005us	5	5	100.00
sideload				20	20	100.00
	kmac_sideload	355.350s	103085.695us	20	20	100.00
app				25	25	100.00
	kmac_app	305.160s	97395.012us	25	25	100.00
app_with_partial_data				10	10	100.00
	kmac_app_with_partial_data	241.080s	197655.068us	10	10	100.00
entropy_refresh				20	20	100.00
	kmac_entropy_refresh	343.330s	319928.006us	20	20	100.00
error				20	20	100.00
	kmac_error	442.240s	172377.646us	20	20	100.00
key_error				20	20	100.00
	kmac_key_error	14.710s	17185.908us	20	20	100.00
sideload_invalid				31	50	62.00
	kmac_sideload_invalid	112.000s	10148.924us	31	50	62.00
edn_timeout_error				20	20	100.00
	kmac_edn_timeout_error	39.060s	5282.406us	20	20	100.00
entropy_mode_error				20	20	100.00
	kmac_entropy_mode_error	36.550s	998.097us	20	20	100.00
entropy_ready_error				10	10	100.00
	kmac_entropy_ready_error	55.680s	17695.596us	10	10	100.00
lc_escalation				50	50	100.00
	kmac_lc_escalation	28.110s	2719.327us	50	50	100.00
stress_all				20	20	100.00
	kmac_stress_all	2395.950s	97959.388us	20	20	100.00
intr_test				10	10	100.00
	kmac_intr_test	1.130s	16.404us	10	10	100.00
alert_test				10	10	100.00
	kmac_alert_test	1.190s	48.600us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	kmac_tl_errors	4.110s	286.048us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	kmac_tl_errors	4.110s	286.048us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	kmac_csr_hw_reset	1.340s	95.193us	1	1	100.00
	kmac_csr_rw	1.540s	68.700us	5	5	100.00
	kmac_csr_aliasing	7.510s	137.796us	1	1	100.00
	kmac_same_csr_outstanding	2.400s	352.613us	5	5	100.00
tl_d_partial_access				12	12	100.00
	kmac_csr_hw_reset	1.340s	95.193us	1	1	100.00
	kmac_csr_rw	1.540s	68.700us	5	5	100.00
	kmac_csr_aliasing	7.510s	137.796us	1	1	100.00
	kmac_same_csr_outstanding	2.400s	352.613us	5	5	100.00

V2S

170/170 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	kmac_shadow_reg_errors	2.740s	536.050us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	kmac_shadow_reg_errors	2.740s	536.050us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	kmac_shadow_reg_errors	2.740s	536.050us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	kmac_shadow_reg_errors	2.740s	536.050us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	kmac_shadow_reg_errors_with_csr_rw	5.960s	912.881us	20	20	100.00
tl_intg_err				30	30	100.00
	kmac_sec_cm	77.810s	31578.735us	5	5	100.00
	kmac_tl_intg_err	5.600s	276.752us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	kmac_tl_intg_err	5.600s	276.752us	25	25	100.00
sec_cm_lc_escalate_en_intersig_mubi				50	50	100.00
	kmac_lc_escalation	28.110s	2719.327us	50	50	100.00
sec_cm_sw_key_key_masking				20	20	100.00
	kmac_smoke	50.760s	3800.459us	20	20	100.00
sec_cm_key_sideload				20	20	100.00
	kmac_sideload	355.350s	103085.695us	20	20	100.00
sec_cm_cfg_shadowed_config_shadow				20	20	100.00
	kmac_shadow_reg_errors	2.740s	536.050us	20	20	100.00
sec_cm_fsm_sparse				5	5	100.00
	kmac_sec_cm	77.810s	31578.735us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	kmac_sec_cm	77.810s	31578.735us	5	5	100.00
sec_cm_packer_ctr_redun				5	5	100.00
	kmac_sec_cm	77.810s	31578.735us	5	5	100.00
sec_cm_cfg_shadowed_config_regwen				20	20	100.00
	kmac_smoke	50.760s	3800.459us	20	20	100.00
sec_cm_fsm_global_esc				50	50	100.00
	kmac_lc_escalation	28.110s	2719.327us	50	50	100.00
sec_cm_fsm_local_esc				5	5	100.00
	kmac_sec_cm	77.810s	31578.735us	5	5	100.00
sec_cm_absorbed_ctrl_mubi				10	10	100.00
	kmac_mubi	225.750s	5274.875us	10	10	100.00
sec_cm_sw_cmd_ctrl_sparse				20	20	100.00
	kmac_smoke	50.760s	3800.459us	20	20	100.00

8/10 passed

80.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				8	10	80.00
	kmac_stress_all_with_rand_reset	216.590s	4075.512us	8	10	80.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=3)				3 test runs
	kmac_sideload_invalid	89808256563858935986905465584613614231062242028091597147279142241610126339348	79	UVM_INFO @ 10020620487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_sideload_invalid	99559045046736491683892787046705021731435402293548981354999897839665233207412	79	UVM_INFO @ 10070397793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_sideload_invalid	106826372726411239291265752399325663815989598891720448217347358573175106481258	79	UVM_INFO @ 10045316401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=8)				2 test runs
	kmac_sideload_invalid	4313967400678975230850520968354955580110839752231685445450893181666853440355	84	UVM_INFO @ 10384040213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_sideload_invalid	53984734017995495751552997224021983669405895514473011569312375266741058165715	86	UVM_INFO @ 10408856475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=5)				2 test runs
	kmac_sideload_invalid	57162233028190331868488250752537286943827108108389248157961937715650435065363	81	UVM_INFO @ 10134732759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_sideload_invalid	7060863833958126561600851296113266451428358656119373437390708792896871382708	81	UVM_INFO @ 10028848871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=2)				2 test runs
	kmac_sideload_invalid	91459341764354193812885552057668816399191584379079633177971921423029204814916	78	UVM_INFO @ 10033950114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_sideload_invalid	75241337770980420459523017943130330293823178299905430460582685363295036832373	78	UVM_INFO @ 10009042791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=7)				2 test runs
	kmac_sideload_invalid	79787425504182066987575498989060254225284463490141144886339948998398217290189	84	UVM_INFO @ 10066831635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_sideload_invalid	16405546881249531190517574110735451957544545963053322976160075879934884280731	84	UVM_INFO @ 10059996485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	kmac_stress_all_with_rand_reset	110029325984551096857118809441462960682565397869536123346465888951948032213874	318	UVM_INFO @ 5432470353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:858) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [] vs [*])				1 test run
	kmac_stress_all_with_rand_reset	77559384905392561443740523591807341667616295948013464268718684949907803589148	210	UVM_INFO @ 8463176640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=4)				1 test run
	kmac_sideload_invalid	51365877340049174477359910015485142582446716884887087616869168738692615448924	80	UVM_INFO @ 10190227384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=16)				1 test run
	kmac_sideload_invalid	61802773624823072868181033225087514470144902202619270302660556790688538053329	93	UVM_INFO @ 10117467530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=15)				1 test run
	kmac_sideload_invalid	91850019503981148701633464331307985453259722286528242313507941340889950922375	92	UVM_INFO @ 10129178319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=11)				1 test run
	kmac_sideload_invalid	108192687734279651556382399074015082106434662946732245920205185185211347922356	87	UVM_INFO @ 10341136208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=9)				1 test run
	kmac_sideload_invalid	97976717632116922475822956978209053876602750640455088211915576834720398435294	87	UVM_INFO @ 10074072413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=25)				1 test run
	kmac_sideload_invalid	14990606353700406160649345918248468719343097464659055288671062971298083492948	104	UVM_INFO @ 11168857774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=21)				1 test run
	kmac_sideload_invalid	100829921625702672442726596805312113983391897053004099861592700294927765659307	97	UVM_INFO @ 10148923512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=18)				1 test run
	kmac_sideload_invalid	51615748318940164583522331531448483686864847256340540256066323828709723179985	95	UVM_INFO @ 10281839618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---