Simulation Results: lc_ctrl/volatile_unlock_disabled

 
06/06/2026 15:22:54 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.43 %
  • code
  • 85.89 %
  • assert
  • 94.97 %
  • func
  • 96.44 %
  • line
  • 97.28 %
  • branch
  • 94.00 %
  • cond
  • 81.34 %
  • toggle
  • 89.54 %
  • FSM
  • 67.29 %
Validation stages
V1
100.00%
V2
99.77%
V2S
100.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 6.320s 832.506us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.210s 15.891us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.490s 20.835us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.230s 495.427us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.860s 35.669us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.710s 86.803us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.490s 20.835us 5 5 100.00
lc_ctrl_csr_aliasing 1.860s 35.669us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 10.220s 172.798us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 19.880s 777.485us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.350s 14.929us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 6.060s 754.358us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 15.750s 1233.744us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 11.460s 1794.235us 20 20 100.00
security_escalation 139 140 99.29
lc_ctrl_state_failure 15.750s 1233.744us 20 20 100.00
lc_ctrl_prog_failure 6.060s 754.358us 20 20 100.00
lc_ctrl_errors 11.460s 1794.235us 20 20 100.00
lc_ctrl_security_escalation 13.270s 1579.021us 20 20 100.00
lc_ctrl_jtag_state_failure 57.440s 2473.069us 20 20 100.00
lc_ctrl_jtag_prog_failure 20.070s 4222.584us 20 20 100.00
lc_ctrl_jtag_errors 103.730s 9460.772us 19 20 95.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 10.790s 1515.702us 20 20 100.00
lc_ctrl_jtag_state_post_trans 31.950s 4356.555us 20 20 100.00
lc_ctrl_jtag_prog_failure 20.070s 4222.584us 20 20 100.00
lc_ctrl_jtag_errors 103.730s 9460.772us 19 20 95.00
lc_ctrl_jtag_access 18.730s 3815.865us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 34.530s 5182.239us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.890s 593.722us 10 10 100.00
lc_ctrl_jtag_csr_rw 4.020s 263.113us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 28.590s 6901.723us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 18.320s 2893.869us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.580s 52.106us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.700s 318.389us 10 10 100.00
lc_ctrl_jtag_alert_test 2.350s 54.346us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 28.730s 2695.786us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.370s 17.537us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 429.820s 30792.556us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.860s 67.254us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 5.080s 255.620us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 5.080s 255.620us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.210s 15.891us 1 1 100.00
lc_ctrl_csr_rw 1.490s 20.835us 5 5 100.00
lc_ctrl_csr_aliasing 1.860s 35.669us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.020s 76.527us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.210s 15.891us 1 1 100.00
lc_ctrl_csr_rw 1.490s 20.835us 5 5 100.00
lc_ctrl_csr_aliasing 1.860s 35.669us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.020s 76.527us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 10.920s 235.273us 5 5 100.00
lc_ctrl_tl_intg_err 4.290s 120.238us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 4.290s 120.238us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 19.880s 777.485us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 15.750s 1233.744us 20 20 100.00
lc_ctrl_sec_cm 10.920s 235.273us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 15.750s 1233.744us 20 20 100.00
lc_ctrl_sec_cm 10.920s 235.273us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 15.750s 1233.744us 20 20 100.00
lc_ctrl_sec_cm 10.920s 235.273us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 15.750s 1233.744us 20 20 100.00
lc_ctrl_sec_cm 10.920s 235.273us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 15.750s 1233.744us 20 20 100.00
lc_ctrl_sec_cm 10.920s 235.273us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 15.750s 1233.744us 20 20 100.00
lc_ctrl_sec_cm 10.920s 235.273us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 15.750s 1233.744us 20 20 100.00
lc_ctrl_sec_cm 10.920s 235.273us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 15.750s 1233.744us 20 20 100.00
lc_ctrl_sec_cm 10.920s 235.273us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 13.270s 1579.021us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 10.220s 172.798us 20 20 100.00
lc_ctrl_jtag_state_post_trans 31.950s 4356.555us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 11.870s 5343.882us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 11.870s 5343.882us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 12.030s 639.262us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.360s 639.718us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.360s 639.718us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
lc_ctrl_stress_all_with_rand_reset 70.240s 9561.811us 4 10 40.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
lc_ctrl_stress_all_with_rand_reset 96704910097958726776160957316381264810541432229917600160281977469360855268028 2394
UVM_INFO @ 11452904519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 43602953528694525314315647274761155973656971647544215723035954018689467530512 151
UVM_INFO @ 108211689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 102889833039464738256711562330322392596725518332351048007765570747672197203176 157
UVM_INFO @ 1565810110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 48560148950431727156663045502322312467639007234862788455499859552390456143779 12771
UVM_INFO @ 1804174470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 73305564993139488230735185465369267829995320028531322102217731700377776867337 6052
UVM_INFO @ 9561811375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 49962956086182938592495881939070693992708838238231479547877330354412175310034 5108
UVM_INFO @ 45330205741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_jtag_errors 13222377251706121172823197413761682198995242837889604249701771546126999912656 738
UVM_INFO @ 723019907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---