Simulation Results: lc_ctrl/volatile_unlock_enabled

 
06/06/2026 15:22:54 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.50 %
  • code
  • 86.13 %
  • assert
  • 95.11 %
  • func
  • 96.26 %
  • line
  • 97.26 %
  • branch
  • 94.09 %
  • cond
  • 81.55 %
  • toggle
  • 89.54 %
  • FSM
  • 68.22 %
Validation stages
V1
100.00%
V2
99.53%
V2S
100.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 3.500s 123.313us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.330s 43.673us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.340s 61.989us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.930s 191.170us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.690s 26.655us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.640s 21.915us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.340s 61.989us 5 5 100.00
lc_ctrl_csr_aliasing 1.690s 26.655us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 9.050s 59.203us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 19.700s 383.884us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.320s 22.986us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 3.850s 152.369us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 12.240s 1179.837us 20 20 100.00
lc_errors 19 20 95.00
lc_ctrl_errors 11.370s 4227.551us 19 20 95.00
security_escalation 138 140 98.57
lc_ctrl_state_failure 12.240s 1179.837us 20 20 100.00
lc_ctrl_prog_failure 3.850s 152.369us 20 20 100.00
lc_ctrl_errors 11.370s 4227.551us 19 20 95.00
lc_ctrl_security_escalation 14.750s 546.749us 20 20 100.00
lc_ctrl_jtag_state_failure 70.380s 23391.875us 20 20 100.00
lc_ctrl_jtag_prog_failure 15.740s 1259.673us 20 20 100.00
lc_ctrl_jtag_errors 63.160s 2876.908us 19 20 95.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 8.600s 641.285us 20 20 100.00
lc_ctrl_jtag_state_post_trans 17.490s 578.170us 20 20 100.00
lc_ctrl_jtag_prog_failure 15.740s 1259.673us 20 20 100.00
lc_ctrl_jtag_errors 63.160s 2876.908us 19 20 95.00
lc_ctrl_jtag_access 17.570s 3786.543us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 19.200s 868.934us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 5.270s 969.845us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.370s 53.350us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 13.360s 4960.881us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 10.710s 4088.759us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.090s 157.615us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.790s 160.747us 10 10 100.00
lc_ctrl_jtag_alert_test 2.180s 423.227us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 12.860s 12104.476us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.660s 26.911us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 340.270s 37772.001us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.650s 74.355us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.690s 156.152us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.690s 156.152us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.330s 43.673us 1 1 100.00
lc_ctrl_csr_rw 1.340s 61.989us 5 5 100.00
lc_ctrl_csr_aliasing 1.690s 26.655us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.120s 146.573us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.330s 43.673us 1 1 100.00
lc_ctrl_csr_rw 1.340s 61.989us 5 5 100.00
lc_ctrl_csr_aliasing 1.690s 26.655us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.120s 146.573us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 9.350s 228.379us 5 5 100.00
lc_ctrl_tl_intg_err 3.850s 542.736us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 3.850s 542.736us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 19.700s 383.884us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 12.240s 1179.837us 20 20 100.00
lc_ctrl_sec_cm 9.350s 228.379us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 12.240s 1179.837us 20 20 100.00
lc_ctrl_sec_cm 9.350s 228.379us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 12.240s 1179.837us 20 20 100.00
lc_ctrl_sec_cm 9.350s 228.379us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 12.240s 1179.837us 20 20 100.00
lc_ctrl_sec_cm 9.350s 228.379us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 12.240s 1179.837us 20 20 100.00
lc_ctrl_sec_cm 9.350s 228.379us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 12.240s 1179.837us 20 20 100.00
lc_ctrl_sec_cm 9.350s 228.379us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 12.240s 1179.837us 20 20 100.00
lc_ctrl_sec_cm 9.350s 228.379us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 12.240s 1179.837us 20 20 100.00
lc_ctrl_sec_cm 9.350s 228.379us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 14.750s 546.749us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 9.050s 59.203us 20 20 100.00
lc_ctrl_jtag_state_post_trans 17.490s 578.170us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 17.450s 765.151us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 17.450s 765.151us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 14.160s 3956.347us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 14.670s 2389.202us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 14.670s 2389.202us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
lc_ctrl_stress_all_with_rand_reset 69.820s 3351.060us 4 10 40.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
lc_ctrl_stress_all_with_rand_reset 12821424860160203728304297444209219138448665042687484356617586953491371016188 4683
UVM_INFO @ 2803921302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 8195405758881630391771935968078930449146493125284640472026815421380023862786 2486
UVM_INFO @ 1471349234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 80971298794055861892608771450887530521505819531456003859656678905854122091664 201
UVM_INFO @ 224536181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 45466064491695854687877509406205518022385348086151354491971177031276846168705 7160
UVM_INFO @ 1493553635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 44306730312500307931379227951470640994876094504230544200192008103622906051975 3010
UVM_INFO @ 1260846126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 3 test runs
lc_ctrl_stress_all_with_rand_reset 79142041307866125556166050891455845031100627065007004271288975783356260300904 3998
UVM_INFO @ 529050242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 44659832979209682616448805971771721989523551921180152308355525397210516314997 4176
UVM_INFO @ 4902878571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 26293063635869115667154998744733473653900474328059690358209929458420062737349 378
UVM_INFO @ 3165110760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---