Simulation Results: otbn

 
06/06/2026 15:22:54 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.66 %
  • code
  • 95.71 %
  • assert
  • 91.27 %
  • func
  • 100.00 %
  • block
  • 99.46 %
  • line
  • 99.59 %
  • branch
  • 93.14 %
  • toggle
  • 90.11 %
  • FSM
  • 100.00 %
Validation stages
V1
99.14%
V2
97.55%
V2S
97.57%
V3
40.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 34.000s 334.500us 1 1 100.00
single_binary 99 100 99.00
otbn_single 83.000s 2177.537us 99 100 99.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 41.000s 51.847us 1 1 100.00
csr_rw 5 5 100.00
otbn_csr_rw 34.000s 45.047us 5 5 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 38.000s 614.692us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 34.000s 18.546us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otbn_csr_mem_rw_with_rand_reset 37.000s 129.227us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otbn_csr_rw 34.000s 45.047us 5 5 100.00
otbn_csr_aliasing 34.000s 18.546us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 131.000s 9010.358us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 83.000s 5219.494us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 66.000s 579.478us 10 10 100.00
multi_error 0 1 0.00
otbn_multi_err 53.000s 441.841us 0 1 0.00
back_to_back 10 10 100.00
otbn_multi 372.000s 1555.878us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 1400.000s 14304.592us 10 10 100.00
lc_escalation 57 60 95.00
otbn_escalate 136.000s 529.013us 57 60 95.00
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 21.000s 33.368us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 31.000s 21.084us 10 10 100.00
alert_test 10 10 100.00
otbn_alert_test 34.000s 52.732us 10 10 100.00
intr_test 10 10 100.00
otbn_intr_test 35.000s 21.417us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otbn_tl_errors 29.000s 107.552us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otbn_tl_errors 29.000s 107.552us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otbn_csr_hw_reset 41.000s 51.847us 1 1 100.00
otbn_csr_rw 34.000s 45.047us 5 5 100.00
otbn_csr_aliasing 34.000s 18.546us 1 1 100.00
otbn_same_csr_outstanding 32.000s 16.981us 5 5 100.00
tl_d_partial_access 12 12 100.00
otbn_csr_hw_reset 41.000s 51.847us 1 1 100.00
otbn_csr_rw 34.000s 45.047us 5 5 100.00
otbn_csr_aliasing 34.000s 18.546us 1 1 100.00
otbn_same_csr_outstanding 32.000s 16.981us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 34.000s 45.250us 10 10 100.00
otbn_dmem_err 39.000s 28.602us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 33.000s 104.749us 5 5 100.00
otbn_controller_ispr_rdata_err 37.000s 62.643us 5 5 100.00
otbn_mac_bignum_acc_err 39.000s 125.272us 5 5 100.00
otbn_urnd_err 19.000s 17.416us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 31.000s 71.092us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 35.000s 13.745us 2 2 100.00
otbn_non_sec_partial_wipe 9 10 90.00
otbn_partial_wipe 34.000s 24.761us 9 10 90.00
tl_intg_err 30 30 100.00
otbn_sec_cm 406.000s 1928.032us 5 5 100.00
otbn_tl_intg_err 40.000s 106.129us 25 25 100.00
passthru_mem_tl_intg_err 5 5 100.00
otbn_passthru_mem_tl_intg_err 81.000s 781.477us 5 5 100.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 406.000s 1928.032us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 406.000s 1928.032us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 34.000s 334.500us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 39.000s 28.602us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 34.000s 45.250us 10 10 100.00
sec_cm_bus_integrity 25 25 100.00
otbn_tl_intg_err 40.000s 106.129us 25 25 100.00
sec_cm_controller_fsm_global_esc 57 60 95.00
otbn_escalate 136.000s 529.013us 57 60 95.00
sec_cm_controller_fsm_local_esc 40 40 100.00
otbn_imem_err 34.000s 45.250us 10 10 100.00
otbn_dmem_err 39.000s 28.602us 15 15 100.00
otbn_zero_state_err_urnd 21.000s 33.368us 5 5 100.00
otbn_illegal_mem_acc 31.000s 71.092us 5 5 100.00
otbn_sec_cm 406.000s 1928.032us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 406.000s 1928.032us 5 5 100.00
sec_cm_scramble_key_sideload 99 100 99.00
otbn_single 83.000s 2177.537us 99 100 99.00
sec_cm_scramble_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 34.000s 45.250us 10 10 100.00
otbn_dmem_err 39.000s 28.602us 15 15 100.00
otbn_zero_state_err_urnd 21.000s 33.368us 5 5 100.00
otbn_illegal_mem_acc 31.000s 71.092us 5 5 100.00
otbn_sec_cm 406.000s 1928.032us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 406.000s 1928.032us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 57 60 95.00
otbn_escalate 136.000s 529.013us 57 60 95.00
sec_cm_start_stop_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 34.000s 45.250us 10 10 100.00
otbn_dmem_err 39.000s 28.602us 15 15 100.00
otbn_zero_state_err_urnd 21.000s 33.368us 5 5 100.00
otbn_illegal_mem_acc 31.000s 71.092us 5 5 100.00
otbn_sec_cm 406.000s 1928.032us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 406.000s 1928.032us 5 5 100.00
sec_cm_data_reg_sw_sca 99 100 99.00
otbn_single 83.000s 2177.537us 99 100 99.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 34.000s 13.170us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 34.000s 39.275us 5 5 100.00
sec_cm_rnd_bus_consistency 4 5 80.00
otbn_rnd_sec_cm 135.000s 668.114us 4 5 80.00
sec_cm_rnd_rng_digest 4 5 80.00
otbn_rnd_sec_cm 135.000s 668.114us 4 5 80.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 35.000s 28.952us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 406.000s 1928.032us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 406.000s 1928.032us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 8 10 80.00
otbn_rf_bignum_intg_err 33.000s 103.993us 8 10 80.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 406.000s 1928.032us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 406.000s 1928.032us 5 5 100.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 30.000s 22.559us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 30.000s 22.559us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 31.000s 16.073us 7 7 100.00
sec_cm_data_mem_sec_wipe 99 100 99.00
otbn_single 83.000s 2177.537us 99 100 99.00
sec_cm_instruction_mem_sec_wipe 99 100 99.00
otbn_single 83.000s 2177.537us 99 100 99.00
sec_cm_data_reg_sw_sec_wipe 99 100 99.00
otbn_single 83.000s 2177.537us 99 100 99.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 372.000s 1555.878us 10 10 100.00
sec_cm_ctrl_flow_count 99 100 99.00
otbn_single 83.000s 2177.537us 99 100 99.00
sec_cm_ctrl_flow_sca 99 100 99.00
otbn_single 83.000s 2177.537us 99 100 99.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 32.000s 66.942us 5 5 100.00
sec_cm_key_sideload 99 100 99.00
otbn_single 83.000s 2177.537us 99 100 99.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 406.000s 1928.032us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
otbn_stress_all_with_rand_reset 607.000s 3120.417us 4 10 40.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 32.000s 71.508us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
otbn_stress_all_with_rand_reset 45745346434979608861382209788489192152630862210365209970992789673115186353939 391
UVM_INFO @ 373486613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 76632186340650338068945954042943153615544543070866596571768345700001455142802 461
UVM_INFO @ 3120417321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 113712042946713010056021514178718889418686787838998696688624990284182178461708 337
UVM_INFO @ 967015245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 79768617960008703330171373847936318589838657179934373512906635750475838670635 233
UVM_INFO @ 332941121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 2 test runs
otbn_multi_err 31234194212091833009555283442166290260529002433994590767809136541809736266152 325
UVM_INFO @ 441840723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rnd_sec_cm 37588512588913181022500860744162836573044340806598253932204267889114276806186 110
UVM_INFO @ 28537214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 2 test runs
otbn_rf_bignum_intg_err 22361895653859683746191208397345796112878547252306894352223240500482364141659 110
UVM_INFO @ 103992520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rf_bignum_intg_err 1108859566328391386107458687477390784349247130408816661584804611767918931839 114
UVM_INFO @ 270727217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 2 test runs
otbn_escalate 101273620980985184804579759089126236013053725528683328698688940424885924450421 114
UVM_ERROR @ 33132578 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 33132578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 27083411893414599410399663594061833152866415824182007915211355844231179509975 115
UVM_ERROR @ 53048192 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 53048192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 111986147306994082736293771039768371597343021051476474051274465462589779881864 269
UVM_INFO @ 5658075201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 18700797030699913417463755188141245415185924033069890598031289989448706397607 290
UVM_INFO @ 2705198860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed 1 test run
otbn_partial_wipe 73582907896320855960048767668001949373397314236402787124304811644814487616397 108
UVM_ERROR @ 4651209 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 4651209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status 1 test run
otbn_escalate 30476644093307968994907908761153368872694957748378740386025813864414712520031 108
UVM_INFO @ 6862185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
otbn_single 82861722348178233380648102062198825066930395168787251377317954678859268595862 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1