Simulation Results: otp_ctrl

 
06/06/2026 15:22:54 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.32 %
  • code
  • 86.14 %
  • assert
  • 95.46 %
  • func
  • 92.37 %
  • line
  • 90.48 %
  • branch
  • 86.94 %
  • cond
  • 94.00 %
  • toggle
  • 95.72 %
  • FSM
  • 63.54 %
Validation stages
V1
96.15%
V2
96.68%
V2S
96.36%
V3
21.78%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.730s 121.802us 1 1 100.00
smoke 10 10 100.00
otp_ctrl_smoke 9.500s 1013.132us 10 10 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.570s 110.592us 1 1 100.00
csr_rw 5 5 100.00
otp_ctrl_csr_rw 1.860s 565.035us 5 5 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.750s 162.879us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 5.260s 387.033us 1 1 100.00
csr_mem_rw_with_rand_reset 4 5 80.00
otp_ctrl_csr_mem_rw_with_rand_reset 4.360s 1764.571us 4 5 80.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otp_ctrl_csr_rw 1.860s 565.035us 5 5 100.00
otp_ctrl_csr_aliasing 5.260s 387.033us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.520s 60.036us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.440s 39.555us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 14.690s 632.549us 1 1 100.00
init_fail 300 300 100.00
otp_ctrl_init_fail 8.090s 2958.133us 300 300 100.00
partition_check 39 60 65.00
otp_ctrl_background_chks 31.720s 3110.251us 10 10 100.00
otp_ctrl_check_fail 29.720s 5502.784us 29 50 58.00
regwen_during_otp_init 30 30 100.00
otp_ctrl_regwen 15.980s 4901.346us 30 30 100.00
partition_lock 30 30 100.00
otp_ctrl_dai_lock 33.520s 4223.962us 30 30 100.00
interface_key_check 10 10 100.00
otp_ctrl_parallel_key_req 28.390s 2565.335us 10 10 100.00
lc_interactions 210 210 100.00
otp_ctrl_parallel_lc_req 22.160s 1647.020us 10 10 100.00
otp_ctrl_parallel_lc_esc 27.500s 9185.701us 200 200 100.00
otp_dai_errors 24 25 96.00
otp_ctrl_dai_errs 56.380s 22995.602us 24 25 96.00
otp_macro_errors 7 10 70.00
otp_ctrl_macro_errs 33.500s 3982.897us 7 10 70.00
test_access 10 10 100.00
otp_ctrl_test_access 29.790s 23168.732us 10 10 100.00
stress_all 10 10 100.00
otp_ctrl_stress_all 552.550s 75026.304us 10 10 100.00
intr_test 10 10 100.00
otp_ctrl_intr_test 2.090s 80.033us 10 10 100.00
alert_test 10 10 100.00
otp_ctrl_alert_test 3.210s 879.308us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otp_ctrl_tl_errors 8.140s 796.036us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otp_ctrl_tl_errors 8.140s 796.036us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otp_ctrl_csr_hw_reset 2.570s 110.592us 1 1 100.00
otp_ctrl_csr_rw 1.860s 565.035us 5 5 100.00
otp_ctrl_csr_aliasing 5.260s 387.033us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.750s 119.412us 5 5 100.00
tl_d_partial_access 12 12 100.00
otp_ctrl_csr_hw_reset 2.570s 110.592us 1 1 100.00
otp_ctrl_csr_rw 1.860s 565.035us 5 5 100.00
otp_ctrl_csr_aliasing 5.260s 387.033us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.750s 119.412us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
otp_ctrl_sec_cm 249.590s 173192.150us 5 5 100.00
tl_intg_err 30 30 100.00
otp_ctrl_sec_cm 249.590s 173192.150us 5 5 100.00
otp_ctrl_tl_intg_err 36.840s 20425.081us 25 25 100.00
prim_count_check 5 5 100.00
otp_ctrl_sec_cm 249.590s 173192.150us 5 5 100.00
prim_fsm_check 5 5 100.00
otp_ctrl_sec_cm 249.590s 173192.150us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
otp_ctrl_tl_intg_err 36.840s 20425.081us 25 25 100.00
sec_cm_secret_mem_scramble 10 10 100.00
otp_ctrl_smoke 9.500s 1013.132us 10 10 100.00
sec_cm_part_mem_digest 10 10 100.00
otp_ctrl_smoke 9.500s 1013.132us 10 10 100.00
sec_cm_dai_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 249.590s 173192.150us 5 5 100.00
sec_cm_kdi_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 249.590s 173192.150us 5 5 100.00
sec_cm_lci_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 249.590s 173192.150us 5 5 100.00
sec_cm_part_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 249.590s 173192.150us 5 5 100.00
sec_cm_scrmbl_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 249.590s 173192.150us 5 5 100.00
sec_cm_timer_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 249.590s 173192.150us 5 5 100.00
sec_cm_dai_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 249.590s 173192.150us 5 5 100.00
sec_cm_kdi_seed_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 249.590s 173192.150us 5 5 100.00
sec_cm_kdi_entropy_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 249.590s 173192.150us 5 5 100.00
sec_cm_lci_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 249.590s 173192.150us 5 5 100.00
sec_cm_part_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 249.590s 173192.150us 5 5 100.00
sec_cm_scrmbl_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 249.590s 173192.150us 5 5 100.00
sec_cm_timer_integ_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 249.590s 173192.150us 5 5 100.00
sec_cm_timer_cnsty_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 249.590s 173192.150us 5 5 100.00
sec_cm_timer_lfsr_redun 5 5 100.00
otp_ctrl_sec_cm 249.590s 173192.150us 5 5 100.00
sec_cm_dai_fsm_local_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 27.500s 9185.701us 200 200 100.00
otp_ctrl_sec_cm 249.590s 173192.150us 5 5 100.00
sec_cm_lci_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 27.500s 9185.701us 200 200 100.00
sec_cm_kdi_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 27.500s 9185.701us 200 200 100.00
sec_cm_part_fsm_local_esc 207 210 98.57
otp_ctrl_parallel_lc_esc 27.500s 9185.701us 200 200 100.00
otp_ctrl_macro_errs 33.500s 3982.897us 7 10 70.00
sec_cm_scrmbl_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 27.500s 9185.701us 200 200 100.00
sec_cm_timer_fsm_local_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 27.500s 9185.701us 200 200 100.00
otp_ctrl_sec_cm 249.590s 173192.150us 5 5 100.00
sec_cm_dai_fsm_global_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 27.500s 9185.701us 200 200 100.00
otp_ctrl_sec_cm 249.590s 173192.150us 5 5 100.00
sec_cm_lci_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 27.500s 9185.701us 200 200 100.00
sec_cm_kdi_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 27.500s 9185.701us 200 200 100.00
sec_cm_part_fsm_global_esc 207 210 98.57
otp_ctrl_parallel_lc_esc 27.500s 9185.701us 200 200 100.00
otp_ctrl_macro_errs 33.500s 3982.897us 7 10 70.00
sec_cm_scrmbl_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 27.500s 9185.701us 200 200 100.00
sec_cm_timer_fsm_global_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 27.500s 9185.701us 200 200 100.00
otp_ctrl_sec_cm 249.590s 173192.150us 5 5 100.00
sec_cm_part_data_reg_integrity 300 300 100.00
otp_ctrl_init_fail 8.090s 2958.133us 300 300 100.00
sec_cm_part_data_reg_bkgn_chk 29 50 58.00
otp_ctrl_check_fail 29.720s 5502.784us 29 50 58.00
sec_cm_part_mem_regren 30 30 100.00
otp_ctrl_dai_lock 33.520s 4223.962us 30 30 100.00
sec_cm_part_mem_sw_unreadable 30 30 100.00
otp_ctrl_dai_lock 33.520s 4223.962us 30 30 100.00
sec_cm_part_mem_sw_unwritable 30 30 100.00
otp_ctrl_dai_lock 33.520s 4223.962us 30 30 100.00
sec_cm_lc_part_mem_sw_noaccess 30 30 100.00
otp_ctrl_dai_lock 33.520s 4223.962us 30 30 100.00
sec_cm_access_ctrl_mubi 30 30 100.00
otp_ctrl_dai_lock 33.520s 4223.962us 30 30 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
otp_ctrl_smoke 9.500s 1013.132us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 30 30 100.00
otp_ctrl_dai_lock 33.520s 4223.962us 30 30 100.00
sec_cm_test_bus_lc_gated 10 10 100.00
otp_ctrl_smoke 9.500s 1013.132us 10 10 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 249.590s 173192.150us 5 5 100.00
sec_cm_direct_access_config_regwen 30 30 100.00
otp_ctrl_regwen 15.980s 4901.346us 30 30 100.00
sec_cm_check_trigger_config_regwen 10 10 100.00
otp_ctrl_smoke 9.500s 1013.132us 10 10 100.00
sec_cm_check_config_regwen 10 10 100.00
otp_ctrl_smoke 9.500s 1013.132us 10 10 100.00
sec_cm_macro_mem_integrity 7 10 70.00
otp_ctrl_macro_errs 33.500s 3982.897us 7 10 70.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 16.280s 8325.162us 1 1 100.00
stress_all_with_rand_reset 21 100 21.00
otp_ctrl_stress_all_with_rand_reset 3600.125s 0.000us 21 100 21.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 39 test runs
otp_ctrl_stress_all_with_rand_reset 1661999579181284170973551105408067457508801884159843776748356562259342881193 25112
UVM_INFO @ 2903554818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 104815777333082181750955759815570948829775099352043024131683482558599511434116 17391
UVM_INFO @ 7474591205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 30140685041684308659157132018325131073487406959368861920724523048851079872563 79537
UVM_INFO @ 6331552495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 105606092910345756024785131035334296950460193897402892274194537673232194298340 11957
UVM_INFO @ 7021644213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 111667390476437615969946559693248537613707194063530464113364975501752272928788 92
UVM_INFO @ 26741357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 112503340303167405221012415650425666017692939729799084126826720138304659393601 9815
UVM_INFO @ 2167985844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 41653659166369724187885358176675120109620267231493077469256106859738116008872 92
UVM_INFO @ 26477987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 59895809138976047231053636968277809692099790522582926456621697500393804545154 31982
UVM_INFO @ 5231797205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 69199121192213729267261956029160694204690025872456281757708134982196136120676 198
UVM_INFO @ 10909181485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 23643173630675049988020451011663934787987301701099773112653331827643727684864 12527
UVM_INFO @ 5201329360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 87540267621170044419105837481574716118662924495756177518189602468105499532043 93
UVM_INFO @ 53478524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 80788023375267691081214428489907359566024900891315040488920003526664570077851 11218
UVM_INFO @ 17474114047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 30540917021916261583366118137503012987945888621359830516861436741106133298349 27428
UVM_INFO @ 4624159030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 88589168003506635323870593781942988001138835530985683273917067086838843060717 224
UVM_INFO @ 984181493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 73090492981509721692800253467900790251851357705643555598794300274979435545310 92
UVM_INFO @ 102576258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 13100731987996030738486432659708079261338334427040004453485207655634221224249 3369
UVM_INFO @ 8217643314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 26791429624079800495856783793575049871843533923863915750867210582435240015836 223
UVM_INFO @ 94264102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 13159556314794730883756831035102425322141830225988162141174341250018530067281 92
UVM_INFO @ 52537459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 112885968320689652536864102948003144228182919356602544324967210056391584481950 14888
UVM_INFO @ 14418429531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 112724323950720961896397904901256119623195669588005086609369911317199280582946 52926
UVM_INFO @ 7579557430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 84146578931805147178106415293870945722888848926344757926748228300297183686461 93
UVM_INFO @ 28792381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 26282079387325240243466482528076026743932627151710184972855744522998902625629 17687
UVM_INFO @ 16084051433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 17787931319611911164103200660100891363052207526281869536379308967809111545021 61256
UVM_INFO @ 2697402247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 21475305416757877507084129203999821851276238137320936963891692020339661488623 4908
UVM_INFO @ 15633942350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 11945690909482655420117739828933401395932539112902091227983089544067962799611 25743
UVM_INFO @ 13434356936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 71101279800447062266818311643518132796172445349629837789762010503131108929548 149
UVM_INFO @ 60641772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 23347925617206859735357850115568730920563275520879662066440938675637117290799 92
UVM_INFO @ 105307023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 68170145841462419579459697981789535882345273070450541106888415781181170282656 92
UVM_INFO @ 54038649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 26733628527890511341550007494486967964735647162272636101455922979090187106019 18587
UVM_INFO @ 2853504196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 76374390630699076529675765586258021048255256560656957922451501185169202185241 18647
UVM_INFO @ 23423885721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 4498744970211296512942948580542383063955298367900975385694513570179703193898 2760
UVM_INFO @ 1202958509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 18182497342811903052166399745550467037628186225948062018649925462966640285032 2690
UVM_INFO @ 426215183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 41049270834083809551808157423606332291040349606885738311019179901097251994335 24943
UVM_INFO @ 2789942839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 83141917320145317013215527522577069729785652337589017475865373979309341317347 28407
UVM_INFO @ 6050988669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 8530696992949393192823345779728898858584981932740232190025454403130706549163 31819
UVM_INFO @ 24993817683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 40970738439966476753555160593315068128639702284466943156641706570046468529791 8808
UVM_INFO @ 5579479134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 80557310135364350435961796549221364878092018887941254334102546197932664597927 92
UVM_INFO @ 103426987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 27407035390900241859562723168800400064487826749310516695642211327464034152673 5416
UVM_INFO @ 55528604054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 27678334541725216141721704731569466935302130334838557841986553526949966424118 1106
UVM_INFO @ 529560455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 38 test runs
otp_ctrl_check_fail 105436934330021563544135231676877102819371821514797098888374903783324257811926 6463
UVM_INFO @ 914689505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 33692321229329240264282041706561322467823225986254103219495613580259202253344 381
UVM_INFO @ 124962314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 111448130676301503075104681393818046541580473133309650151864543088545863975591 3083
UVM_INFO @ 1631090740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 76660308906905509759157907604776708158425628388628664202329086755043873746146 12070
UVM_INFO @ 7972001951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 41189139631502798844871997495859551666639136583887278482096835556678059300541 3230
UVM_INFO @ 1750459284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 32479246074091992420889524592365606929362795447911533966097799051258049435195 11610
UVM_INFO @ 2506154545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 10266782918816653697648582679545981022979458301467098827877291355309203710948 14148
UVM_INFO @ 498200932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 21808711635494698838811988116522103472362455522537349066567261329810235430312 3201
UVM_INFO @ 2651406715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 106937312856921793626226822744254802482249345533225024625083465626071072761070 503
UVM_INFO @ 152022244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 35247279741816468057379470222096665818085039399864402527039975561055543984628 5260
UVM_INFO @ 609028483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 51365923135552019347249480650823725449322924689748486678821674575997547976087 7255
UVM_INFO @ 15096023761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 64606741906871621508666072694998667551315964699904453855848949822274328018072 9990
UVM_INFO @ 945566603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 103717096446474263901926572247199890123859848024627747422138595776281164212317 641
UVM_INFO @ 83766856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 50452171514554841196667224596955975202691726460086789977462792364088921587696 695
UVM_INFO @ 68939113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 113531809057802524619173852491769493620015863945467235079343089477727106772197 773
UVM_INFO @ 238319653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 55163921688873748219846252242824368134541459592616190719419714639140068625428 4096
UVM_INFO @ 1876094495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 87488364477738966266412823722454001622157440487199888273316629258912382838641 10227
UVM_INFO @ 1090125771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 92244347423332326569479569158695070279750565659934596873734082533138172398773 5577
UVM_INFO @ 861565035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 89646838167307327218678477769300875312681587765003009657303456228890666953725 11783
UVM_INFO @ 1789286238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 81564285940447988017242456840386301901690585139377867812011083087781716538681 28607
UVM_INFO @ 19472001578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 60353771229127434807078902604238598818950738616004770049613478460088819058673 3244
UVM_INFO @ 498242572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 66132786989766839713038918660983510220609849908985869232929496915783650228457 3612
UVM_INFO @ 479178574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 61707238907221971508654399845735509977091823175906463939568063291304207781704 10360
UVM_INFO @ 892815118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 6087594440509381928055229275247066805093007770671765316813268201920141105316 1845
UVM_INFO @ 119509550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 8182317452226518032474731346605949922068554812938259564782933852074565718614 3315
UVM_INFO @ 1529629489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 42881533903383521269363039320842218698825670671178796748770066333930566191941 812
UVM_INFO @ 518120791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 93936138044912480486707140551564816099470797135440389364379993640264231336263 5348
UVM_INFO @ 182915111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 108861057021202498990600938532798803843868028928296146974395434271050856493601 111
UVM_INFO @ 177676699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 67223636735177121123465374858944978866872085587193768981364043214075109073852 16600
UVM_INFO @ 9952445575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 75258380790491361927906381818569106070860868755135607336555681478924832512409 5937
UVM_INFO @ 8862106774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 17079344514433151866680785304184232063680401818466556911039367798814916488006 151
UVM_INFO @ 37916751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 74824596812521077715565230996548999239815133196202950008234806393954057426803 9549
UVM_INFO @ 1553202841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 30546997495854792067380578833998786842377253435807210063510881777267733898217 8445
UVM_INFO @ 3040239242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 30254524576554240365171946462617721736748113955017089204147256190139822986384 24971
UVM_INFO @ 963547516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 73604712747591110890012983703511898481486426792674066563633412482626033792689 2175
UVM_INFO @ 2460804209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 99688128565732042365141695694276353931410987633042698472353651772778448467958 533
UVM_INFO @ 109630092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 51696749271553343501843839989803848350105408895263294592465377704232221754824 319
UVM_INFO @ 161576354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 25122905250679857113522571709480513379854736847290644212071491807316291140934 19968
UVM_INFO @ 374474384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 11 test runs
otp_ctrl_stress_all_with_rand_reset 85215513527917478612014164753289794685793463766649202007797119032168537443292 92
UVM_INFO @ 102622319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 96983235928232895576098714599811918229241698603081657834269911680141862448772 137
UVM_INFO @ 545774142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 42862158027501121005088022676511243830097271360978274367986552648087105675867 92
UVM_INFO @ 432634226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 39434225168156967643542627178331547830876468174301360266515074077267805314151 18421
UVM_INFO @ 943299228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 11922654003515614859982196833691679043263669716051718786663754811001772866622 1488
UVM_INFO @ 95942626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 80171277341289035208416474703526455376257977674522011986552237693106144979297 18532
UVM_INFO @ 3408331400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 97520673658393832234968998832562379625952631136629578264125901861827055013371 26707
UVM_INFO @ 2427387434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 113188821409970778431091075239656368467442599893189657611196842099769737671957 2336
UVM_INFO @ 7545969363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 104545471767683169319187312633030589116093799060741061036919851237431795798781 27960
UVM_INFO @ 8726833814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 72205336932706258350101663063227278847098574569504686084062474596898771015608 92
UVM_INFO @ 52290183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 43342725482336767894997586528069169091866357417872830614476291854473446592108 6123
UVM_INFO @ 5140058394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 10 test runs
otp_ctrl_stress_all_with_rand_reset 8663366037175737518462262550873649300851083812407396673563666336141084935999 10984
UVM_INFO @ 3297166813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 52355180442139112966921532071880093654284886207885132124960116067063711020375 111
UVM_INFO @ 39256100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 86802464535162176108933743191925786128534743053754695044305859147782001496554 25944
UVM_INFO @ 8026920457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 50354312925334607925356412513866496365481548338243745940609522531881728181895 555
UVM_INFO @ 746408298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 17019017098662142841235513656736762862069499830167517558323217252222744921441 6956
UVM_INFO @ 2650740286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 4868685709302942744667948571640216880678104732072242038815882867647014783441 5918
UVM_INFO @ 26996116878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 18837012410575479070051194618400809771144929592836683153109387228186287538776 5979
UVM_INFO @ 1993138519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 113386609210021704232438732126010055602377051786308094380089220898263135099171 11895
UVM_INFO @ 28486585158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 21967562720404936162637805557554923254835882486074665108437119904901468481381 2940
UVM_INFO @ 1231952979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 4682660457618766778198138295018391042767725786286053191841125058028470884768 10343
UVM_INFO @ 1018632378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(cio_test_en_o == *)' 2 test runs
otp_ctrl_csr_mem_rw_with_rand_reset 26284429460456626404674659409230750155818058774830312409630798661344180581966 93
UVM_ERROR @ 54325505 ps: (otp_ctrl_if.sv:297) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 54325505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 99393353573430886870472527463088848250041733091098158131186339860807758777386 3596
UVM_ERROR @ 501362956 ps: (otp_ctrl_if.sv:297) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 501362956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed 2 test runs
otp_ctrl_stress_all_with_rand_reset 26500112932968124105458805256814366724204110879680810733223010092070736944950 6243
UVM_INFO @ 1196332277 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 1196426030 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 1196769791 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 1196811459 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
otp_ctrl_stress_all_with_rand_reset 63167594991093602075429217266888631159280641588193415727530752963401356042055 4426
UVM_INFO @ 14889954453 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 14891621123 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 14897287801 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 14898287803 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
Job timed out after * minutes 1 test run
otp_ctrl_stress_all_with_rand_reset 13257614087581981031614541444678530221547758992922112240237112131463636581646 None
UVM_ERROR (cip_base_vseq.sv:1286) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otp_ctrl_stress_all_with_rand_reset 6737125576137391053274318854691738934830344965435133109327236090958957689182 24899
UVM_INFO @ 34368562579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 51441602669894868205835692644998258382065283814110318167840476638207881976041 17802
UVM_INFO @ 19602907233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---