| V1 |
|
100.00% |
| V2 |
|
80.16% |
| V2S |
|
100.00% |
| V3 |
|
2.00% |
| unmapped |
|
88.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 50 | 50 | 100.00 | |||
| pattgen_smoke | 3.000s | 232.794us | 50 | 50 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| pattgen_csr_hw_reset | 2.000s | 17.102us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| pattgen_csr_rw | 1.000s | 12.024us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| pattgen_csr_bit_bash | 3.000s | 320.711us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| pattgen_csr_aliasing | 1.000s | 31.541us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| pattgen_csr_mem_rw_with_rand_reset | 2.000s | 68.277us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| pattgen_csr_rw | 1.000s | 12.024us | 5 | 5 | 100.00 | |
| pattgen_csr_aliasing | 1.000s | 31.541us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| perf | 27 | 50 | 54.00 | |||
| pattgen_perf | 3602.162s | 0.000us | 27 | 50 | 54.00 | |
| cnt_rollover | 50 | 50 | 100.00 | |||
| cnt_rollover | 80.000s | 9075.281us | 50 | 50 | 100.00 | |
| error | 50 | 50 | 100.00 | |||
| pattgen_error | 2.000s | 301.640us | 50 | 50 | 100.00 | |
| stress_all | 22 | 50 | 44.00 | |||
| pattgen_stress_all | 10801.000s | 0.000us | 22 | 50 | 44.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| pattgen_alert_test | 1.000s | 10.438us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| pattgen_intr_test | 2.000s | 10.359us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| pattgen_tl_errors | 3.000s | 113.451us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| pattgen_tl_errors | 3.000s | 113.451us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| pattgen_csr_hw_reset | 2.000s | 17.102us | 1 | 1 | 100.00 | |
| pattgen_csr_rw | 1.000s | 12.024us | 5 | 5 | 100.00 | |
| pattgen_csr_aliasing | 1.000s | 31.541us | 1 | 1 | 100.00 | |
| pattgen_same_csr_outstanding | 2.000s | 19.591us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| pattgen_csr_hw_reset | 2.000s | 17.102us | 1 | 1 | 100.00 | |
| pattgen_csr_rw | 1.000s | 12.024us | 5 | 5 | 100.00 | |
| pattgen_csr_aliasing | 1.000s | 31.541us | 1 | 1 | 100.00 | |
| pattgen_same_csr_outstanding | 2.000s | 19.591us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| pattgen_tl_intg_err | 2.000s | 273.209us | 25 | 25 | 100.00 | |
| pattgen_sec_cm | 2.000s | 60.618us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| pattgen_tl_intg_err | 2.000s | 273.209us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 50 | 2.00 | |||
| pattgen_stress_all_with_rand_reset | 136.000s | 21643.543us | 1 | 50 | 2.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 44 | 50 | 88.00 | |||
| pattgen_inactive_level | 266.000s | 10018.376us | 44 | 50 | 88.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_base_vseq.sv:1287) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 47 test runs | |||
| pattgen_stress_all_with_rand_reset | 85329013483633158770514970927738847635828704461583954690751709776847050901668 | 151 |
UVM_ERROR @ 1068498236 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1068498236 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 1069248233 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 71291403889056294014821194121207987481374694433842937110363960920784989307469 | 121 |
UVM_ERROR @ 2314717386 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2314717386 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 2315102006 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 33856272770627941501219029755572650263208403378834148130501094225285877256122 | 136 |
UVM_ERROR @ 3887308771 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3887308771 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 3887626956 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 49069017402523250706247400823194678918807631161367405912663163316823982628998 | 173 |
UVM_ERROR @ 519176548 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 519176548 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 519228093 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 35820864949090059727877986818535221985375385493021414066616220565207340179569 | 353 |
UVM_ERROR @ 2650717358 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2650717358 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 5/5
UVM_INFO @ 2650769443 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 74290653441902362846844149817320517108419528749376296600478113699776238409413 | 172 |
UVM_ERROR @ 529722442 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 529722442 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/5
UVM_INFO @ 529889110 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 115485998524399140284153507902874382485137009859508107878141988521117609293028 | 126 |
UVM_ERROR @ 2375421439 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2375421439 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 2375469059 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 31938717042399521101871725964028655950292564561387851768330971861101083240502 | 183 |
UVM_ERROR @ 6008848854 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 6008848854 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 6009134568 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 88168407278290290892162232613543458043375512261779376322916832620139840314675 | 113 |
UVM_ERROR @ 124147939 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 124147939 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 124170411 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 95707910509291885786078724105123528601632557991921243852505763418422744863413 | 124 |
UVM_ERROR @ 4663468227 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4663468227 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 4663918227 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 91229292997652004528864203063796773117346537291497743571642296217941092493727 | 224 |
UVM_ERROR @ 1462537111 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1462537111 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 1462597111 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 108164315315729000113207767608454639880423252366749705186556655735663861243453 | 143 |
UVM_ERROR @ 1130231980 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1130231980 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 1130325733 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 39352098408074870851290888838741215472897521721965194235723250569716791576250 | 189 |
UVM_ERROR @ 1972700663 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1972700663 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 1973100663 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 94763035920575559069481963472575927323272033301716980214208846809874340570524 | 184 |
UVM_ERROR @ 5569859023 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 5569859023 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 5569996955 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 1863496210897064714658444350038306926326961380005812385727441385482066390174 | 118 |
UVM_ERROR @ 867468012 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 867468012 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 867560793 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 44578670746259175990732118964383066422662508164490974859900563646424890092996 | 288 |
UVM_ERROR @ 1658237290 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1658237290 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 6/10
UVM_INFO @ 1658310209 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 63168783296526819500703368364489267130352524197434578037073261567607538017937 | 199 |
UVM_ERROR @ 333184827 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 333184827 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/5
UVM_INFO @ 333284827 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 51989671368258782199630346216087647059225295984024591714547547972242764585181 | 149 |
UVM_ERROR @ 2362469501 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2362469501 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 2362761170 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 79635615614033487313669891852066597993749316381074012308642243297724063456198 | 125 |
UVM_ERROR @ 3785699047 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3785699047 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 3785929819 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 869122171598466426889289645066631082353084305582793652060013679102985585371 | 212 |
UVM_ERROR @ 2272904501 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2272904501 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 2273019887 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 55517794910650344850546398905803143086534780205704355460845949496665731593486 | 117 |
UVM_ERROR @ 9317171262 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 9317171262 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 9317837928 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 16316319049273411260682412927509701195975176529717277729988708590331991027057 | 114 |
UVM_ERROR @ 910069451 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 910069451 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 910402787 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 73813162532388924182276261681863223584943352239141216637744399430716844208993 | 209 |
UVM_ERROR @ 803862632 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 803862632 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 803957366 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 110655572464832531560913465482313675603467247175401228873080305153656693947814 | 146 |
UVM_ERROR @ 573770687 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 573770687 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 573800687 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 47251633735132477032374159566670283118390000774492299444910025444212240803449 | 120 |
UVM_ERROR @ 950038388 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 950038388 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 950225885 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 51576274267116902588723905272438055653543858073018536836101938861614160719942 | 165 |
UVM_ERROR @ 3975972665 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3975972665 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 3976347668 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 100972618287476006780582112785800612599547041838308171430178173620878788877244 | 276 |
UVM_ERROR @ 6542580488 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 6542580488 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 5/10
UVM_INFO @ 6542747156 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 7463019817727145329737591823521973641505728771096769666944845584301482899042 | 246 |
UVM_ERROR @ 2025459592 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2025459592 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/10
UVM_INFO @ 2025565972 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 107113697644669963521747029013978598275231250597305086573124507974937792085559 | 184 |
UVM_ERROR @ 1565445064 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1565445064 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/5
UVM_INFO @ 1565515064 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 97247584657347466033487078333048658291274649120779682258945149860446472015440 | 128 |
UVM_ERROR @ 500294415 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 500294415 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 500314415 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 16501731010431166817662493323612413386244335486740829185371994903265021380185 | 153 |
UVM_ERROR @ 1091605639 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1091605639 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 1091645639 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 28607399719317246645426262502109083337283868128430862819588280622975386324715 | 147 |
UVM_ERROR @ 861585056 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 861585056 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 861624272 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 40254562171813775495967049687490223614537238088794154469007485494715174436055 | 180 |
UVM_ERROR @ 1078003546 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1078003546 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 1078053546 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 95772377971448095458327371426213866164021436494797712256303658180963699691135 | 115 |
UVM_ERROR @ 3569430258 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3569430258 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 3569742758 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 78933802561649810946280352622848154405146979490398651045440973407177329569309 | 382 |
UVM_ERROR @ 11146556098 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 11146556098 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 6/10
UVM_INFO @ 11146639432 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 77623801675740863846589255216304571553889897742726234642395998954416707308530 | 151 |
UVM_ERROR @ 1009254479 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1009254479 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 1009462814 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 110033283661378869866560629486368068921828003314375048313582811439648674589685 | 143 |
UVM_ERROR @ 136799721 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 136799721 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 136851266 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 63728049756529036460324781149823239997838156202182378304207888151251887758135 | 113 |
UVM_ERROR @ 742277744 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 742277744 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 742402745 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 45339271633855602598029779329897781750780909817062864593771189994758903934931 | 124 |
UVM_ERROR @ 193575680 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 193575680 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 193656488 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 93492287214495213344021581567918449020684196244636866690802900963876072099811 | 282 |
UVM_ERROR @ 2266532861 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2266532861 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 2266562861 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 96168478014514214792823940281226274156853111809887840665081483902469934353015 | 113 |
UVM_ERROR @ 1808465977 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1808465977 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 1808799311 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 18959220636899655499227222179374744964908579523808009925838404311383677626675 | 362 |
UVM_ERROR @ 3271478858 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3271478858 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 6/10
UVM_INFO @ 3271540082 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 115526315728445712003109817234512169585313482236395074518987319080343295986725 | 159 |
UVM_ERROR @ 1607289949 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1607289949 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 1607539951 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 59594490626634751896576427732251387763897066064242407443139852244775718823610 | 143 |
UVM_ERROR @ 2357846657 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2357846657 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 2358054987 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 36558063814703413044146985408424316769113316155569016500554486246577025706165 | 149 |
UVM_ERROR @ 607589864 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 607589864 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 607869864 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 52439014901559968022067042322165086047430949303499264745572326851180133381991 | 114 |
UVM_ERROR @ 251201066 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 251201066 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 251271773 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 104688716711832299675230900895947896072586922689994907769582475599029723533128 | 292 |
UVM_ERROR @ 8118024760 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 8118024760 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 5/10
UVM_INFO @ 8118191428 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: | 22 test runs | |||
| pattgen_stress_all | 61654703716742608567737740303646964000330187645851601260167068762582821957751 | 143 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11175
|
|
| pattgen_stress_all | 55817611801629420194719146228585983585771249282541358201108193912002785581543 | 152 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11302
|
|
| pattgen_stress_all | 85563821883146130500616575670202695235441950837549358797281670024550388401592 | 151 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11077
|
|
| pattgen_stress_all | 15592339868363389647910197653320605429288095680179269373234363171319017061604 | 125 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11107
|
|
| pattgen_stress_all | 49781303470806049642109987941083806490438397004716686177331117758050140239290 | 133 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11131
|
|
| pattgen_stress_all | 106807337458587870341282654191269758855851324288488280388813650180955236294969 | 125 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11108
|
|
| pattgen_stress_all | 7070722440884805928796605962824351096712298881194863064191102545169572814149 | 159 |
--------------------------------------
Name Type Size Value
--------------------------------------
exp_item pattgen_item - @11152
|
|
| pattgen_stress_all | 95162359993917298843673620137212897625089956432908260999248236019335102440524 | 132 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11139
|
|
| pattgen_stress_all | 12135511015007348993651120770296499377388031533201684066209290974426093444641 | 155 |
----------------------------------------
Name Type Size Value
----------------------------------------
exp_item pattgen_item - @11253
|
|
| pattgen_stress_all | 7059884627169341123576303124557702506733821577003925971955753155835298402082 | 137 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11126
|
|
| pattgen_stress_all | 75375281544315276116310084942188769521003680745213966571165203338563878633334 | 148 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11078
|
|
| pattgen_stress_all | 2971976463664428074059267443928144493174566351539707068492047014778758323813 | 130 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11042
|
|
| pattgen_stress_all | 103424385002421687145501074566744582984692968687232000118756295033645544206021 | 155 |
----------------------------------------
Name Type Size Value
----------------------------------------
exp_item pattgen_item - @11065
|
|
| pattgen_stress_all | 50741538510381483329418145304845270061301492763523193185606514781328905228964 | 143 |
--------------------------------------
Name Type Size Value
--------------------------------------
exp_item pattgen_item - @11140
|
|
| pattgen_stress_all | 113235126964064339462735209971879192914251943299778346165656509169799960661056 | 149 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11200
|
|
| pattgen_stress_all | 112556823369280910864424872209196930838276858673676910878873352191184673558196 | 132 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11118
|
|
| pattgen_stress_all | 65859796724710286166332680566384269358391001522292440487188448452812965473447 | 150 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11161
|
|
| pattgen_stress_all | 89302306205474890141187318091715352433715429279091482395282590220406795507279 | 148 |
----------------------------------------
Name Type Size Value
----------------------------------------
exp_item pattgen_item - @11120
|
|
| pattgen_stress_all | 82002662915287223923823005920575744706300729093325354452960877489099044628576 | 135 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11126
|
|
| pattgen_stress_all | 24346729885860904540719288536061988045279752410018278221278170179151545861066 | 138 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11117
|
|
| pattgen_stress_all | 35938584395702637876697176755984344439483349239096508859581532850886168342931 | 156 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11136
|
|
| pattgen_stress_all | 83336065345771957605015240873475774968317771122420117106018784134423914402539 | 125 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11075
|
|
| Job timed out after * minutes | 19 test runs | |||
| pattgen_perf | 40019548747580059334288477050930091309182573800937222481297173009205038796745 | None | ||
| pattgen_stress_all | 48428220779128570772689827239862367361790011705442233191766686979835547907566 | None | ||
| pattgen_perf | 33813960062555261867792148691674283886980565722341043324270769139811709934188 | None | ||
| pattgen_stress_all | 55969673220564301458356550943088310932037619243285751443543726401961487061129 | None | ||
| pattgen_perf | 88008580966742029134507563460914141419614930035679570936709438554106682015621 | None | ||
| pattgen_stress_all | 19932409506154696571169580059174684892234788504483161223559257147122234611590 | None | ||
| pattgen_perf | 42963233556353106529754616984730177041263035116832484389127216689413433778586 | None | ||
| pattgen_perf | 65271288810842600622478713186618595318500270133089741140004822451244836210273 | None | ||
| pattgen_perf | 39104079734982200198503649826222573733629234837835769345740982753883744234870 | None | ||
| pattgen_perf | 48454026021822941659356708066564783364688207294055511373222490692363210632253 | None | ||
| pattgen_stress_all | 86706479153223919918447050530784636435910163981943416452840580144081238809290 | None | ||
| pattgen_perf | 950717414969133385112661446856246017080187307646183760798445332582233230515 | None | ||
| pattgen_perf | 99518913647882742472481185131969160129923070360985590479383862682444555115851 | None | ||
| pattgen_perf | 37116690865235875440934418658340998818708171743031666345286369195951297298703 | None | ||
| pattgen_perf | 40828220692152561610756407755889197051465900033369028159615525424035880047287 | None | ||
| pattgen_perf | 72615751676131067178956560965532886917504931300121610120664817333589308193931 | None | ||
| pattgen_stress_all | 63902940845814057470564419829975937258556870025224872813527265129914247632905 | None | ||
| pattgen_perf | 32252839925998670523077476789296200108367296041633797860702863452846458408666 | None | ||
| pattgen_perf | 88739804895151320133499546052839727163074539380084804955498716796375438816098 | None | ||
| UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | 10 test runs | |||
| pattgen_perf | 2643192452017294921894505301015499118637806115489255508103765836410811382075 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 113824170558556126075139096854038778241433395423405521430281586326336044183372 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 80046167396678528240051426597890653512800936174696458808651080497735965274737 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 107610176482149823323620734839971720522497937205551575346592738060226682150605 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 51217062012400000217221834748466952164705384804035291785454432985391965308885 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 80258050370503280725419556012095700500548450813145439384713824846123711749307 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 12067912033590750708504823479642991965603000465308789281384720316366108243227 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_stress_all | 52793373490501075163699702740229638699664783015846987106247926858838647293643 | 121 |
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 78534457386899857741675533737224940547464376056275684435704574686407870508893 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 63975590918635238308096020150280352759438894803425618886734613930380752041784 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard] | 2 test runs | |||
| pattgen_stress_all_with_rand_reset | 37475114344308292209004987482806284412290859922121750197339198247676997590942 | 135 |
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
|
|
| pattgen_stress_all_with_rand_reset | 98439481563303465611676889109450216657193552182235398994618112892387928500454 | 128 |
--> channel 1 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) | 1 test run | |||
| pattgen_inactive_level | 28018551084976315541080475911621664241155724999172630597678228608775840518516 | 99 |
UVM_INFO @ 10018375613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) | 1 test run | |||
| pattgen_inactive_level | 49347984418819471915840143240474379674900038711640597807854122927792684988549 | 99 |
UVM_INFO @ 10023596413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=30) | 1 test run | |||
| pattgen_inactive_level | 99336143896787979196421770070300710282118775279913749242560084851479526149113 | 99 |
UVM_INFO @ 10051123292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) | 1 test run | |||
| pattgen_inactive_level | 11482980307740780575582662284226610650407862697470862066511940208508643667644 | 99 |
UVM_INFO @ 10001656460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) | 1 test run | |||
| pattgen_inactive_level | 45938902418742988097022498396635367686892866809045696608436884243841795881688 | 99 |
UVM_INFO @ 10136963959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) | 1 test run | |||
| pattgen_inactive_level | 98183096771820907384156879026398949874000482240643857064482065376368347637683 | 99 |
UVM_INFO @ 10111594592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|