Simulation Results: pwrmgr

 
06/06/2026 15:22:54 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.51 %
  • code
  • 97.57 %
  • assert
  • 98.96 %
  • func
  • 99.01 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 96.75 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
91.97%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
pwrmgr_smoke 0.980s 23.835us 10 10 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.990s 60.471us 1 1 100.00
csr_rw 5 5 100.00
pwrmgr_csr_rw 1.010s 47.430us 5 5 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.600s 163.512us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.250s 96.292us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.630s 43.227us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
pwrmgr_csr_rw 1.010s 47.430us 5 5 100.00
pwrmgr_csr_aliasing 1.250s 96.292us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 10 10 100.00
pwrmgr_wakeup 1.610s 232.542us 10 10 100.00
control_clks 10 10 100.00
pwrmgr_wakeup 1.610s 232.542us 10 10 100.00
aborted_low_power 20 20 100.00
pwrmgr_aborted_low_power 1.160s 110.148us 10 10 100.00
pwrmgr_lowpower_invalid 1.070s 42.136us 10 10 100.00
reset 14 20 70.00
pwrmgr_reset 3.660s 1000.000us 8 10 80.00
pwrmgr_reset_invalid 1.220s 111.284us 6 10 60.00
main_power_glitch_reset 8 10 80.00
pwrmgr_reset 3.660s 1000.000us 8 10 80.00
reset_wakeup_race 10 10 100.00
pwrmgr_wakeup_reset 1.340s 206.592us 10 10 100.00
lowpower_wakeup_race 10 10 100.00
pwrmgr_lowpower_wakeup_race 1.290s 338.564us 10 10 100.00
disable_rom_integrity_check 8 10 80.00
pwrmgr_disable_rom_integrity_check 2.860s 1000.000us 8 10 80.00
stress_all 7 10 70.00
pwrmgr_stress_all 20.030s 10364.711us 7 10 70.00
intr_test 10 10 100.00
pwrmgr_intr_test 0.980s 23.768us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
pwrmgr_tl_errors 2.810s 359.140us 25 25 100.00
tl_d_illegal_access 25 25 100.00
pwrmgr_tl_errors 2.810s 359.140us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
pwrmgr_csr_hw_reset 0.990s 60.471us 1 1 100.00
pwrmgr_csr_rw 1.010s 47.430us 5 5 100.00
pwrmgr_csr_aliasing 1.250s 96.292us 1 1 100.00
pwrmgr_same_csr_outstanding 1.280s 147.070us 5 5 100.00
tl_d_partial_access 12 12 100.00
pwrmgr_csr_hw_reset 0.990s 60.471us 1 1 100.00
pwrmgr_csr_rw 1.010s 47.430us 5 5 100.00
pwrmgr_csr_aliasing 1.250s 96.292us 1 1 100.00
pwrmgr_same_csr_outstanding 1.280s 147.070us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
pwrmgr_tl_intg_err 1.990s 207.859us 25 25 100.00
pwrmgr_sec_cm 2.740s 608.738us 5 5 100.00
prim_count_check 5 5 100.00
pwrmgr_sec_cm 2.740s 608.738us 5 5 100.00
prim_fsm_check 5 5 100.00
pwrmgr_sec_cm 2.740s 608.738us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
pwrmgr_tl_intg_err 1.990s 207.859us 25 25 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.510s 792.262us 10 10 100.00
sec_cm_rom_ctrl_intersig_mubi 20 20 100.00
pwrmgr_wakeup_reset 1.340s 206.592us 10 10 100.00
pwrmgr_repeat_wakeup_reset 2.880s 920.228us 10 10 100.00
sec_cm_rstmgr_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 1.400s 75.542us 10 10 100.00
sec_cm_esc_rx_clk_bkgn_chk 10 10 100.00
pwrmgr_esc_clk_rst_malfunc 0.990s 29.108us 10 10 100.00
sec_cm_esc_rx_clk_local_esc 5 5 100.00
pwrmgr_sec_cm 2.740s 608.738us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
pwrmgr_sec_cm 2.740s 608.738us 5 5 100.00
sec_cm_fsm_terminal 5 5 100.00
pwrmgr_sec_cm 2.740s 608.738us 5 5 100.00
sec_cm_ctrl_flow_global_esc 10 10 100.00
pwrmgr_global_esc 0.970s 96.174us 10 10 100.00
sec_cm_main_pd_rst_local_esc 10 10 100.00
pwrmgr_glitch 1.010s 40.457us 10 10 100.00
sec_cm_ctrl_config_regwen 10 10 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.470s 240.160us 10 10 100.00
sec_cm_wakeup_config_regwen 5 5 100.00
pwrmgr_csr_rw 1.010s 47.430us 5 5 100.00
sec_cm_reset_config_regwen 5 5 100.00
pwrmgr_csr_rw 1.010s 47.430us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 6 10 60.00
pwrmgr_escalation_timeout 1.280s 106.020us 6 10 60.00
stress_all_with_rand_reset 10 10 100.00
pwrmgr_stress_all_with_rand_reset 12.260s 3826.194us 10 10 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 4 test runs
pwrmgr_reset 22976810290641629771276309576404865787030844926295066677912897331262227308354 104
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 61225855563562564998825588020281447743705047631653641008255188842518280519041 144
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 64962934869941581297689217855329984064920099240428497863677237559275864380159 141
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_reset 84855738645396669065264384836685633899996982552489772968861329996800920235874 91
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 3 test runs
pwrmgr_stress_all 44467796076169650943304267539573761653875698156295907499019374409438015128994 234
UVM_INFO @ 10364710831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 64546311505275834147053413762568903173541851398071391760298566543789941371428 456
UVM_INFO @ 11962460448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 25859361736080220522401848313079979527229153341926024673781205028545629463267 96
UVM_INFO @ 10027552317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!clk_en) || status)' 3 test runs
pwrmgr_escalation_timeout 79347795397501342276695824098915816165086379534421789873979584499127561986689 79
UVM_ERROR @ 106020459 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 106020459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 20486548626145169994144836595067112081174171615622972840586163361027641998483 79
UVM_ERROR @ 264289710 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 264289710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 79814791067310339849775688037674101616418038625342754128452405430063324575184 79
UVM_ERROR @ 96302442 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 96302442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitResetPrep 2 test runs
pwrmgr_reset_invalid 9930178625976752964655270492340147235769496397352933128639580622471028003618 84
UVM_INFO @ 44146038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_reset_invalid 73850673698048264120726286153923264049542790416552939867650640717774314953510 93
UVM_INFO @ 41736242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(clk_en || (!status))' 1 test run
pwrmgr_escalation_timeout 78342420180571303038401288378321218953643056580366729218698735352797588060178 79
UVM_ERROR @ 98628886 ps: (clkmgr_pwrmgr_sva_if.sv:34) [ASSERT FAILED] StatusFall_A
UVM_INFO @ 98628886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitEnableClocks 1 test run
pwrmgr_reset_invalid 54294760136341846547510906598346994006896376184703271081336144753855236141404 101
UVM_INFO @ 57298904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitStrap 1 test run
pwrmgr_reset_invalid 65419547056935634683075316653001729322529204940291200501052249777401452827785 125
UVM_INFO @ 106624228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---