Simulation Results: rom_ctrl/32kb

 
06/06/2026 15:22:54 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.88 %
  • code
  • 99.68 %
  • assert
  • 97.67 %
  • func
  • 99.28 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.22%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 5.140s 319.454us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.810s 172.206us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 7.360s 2080.585us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.130s 165.984us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.710s 171.327us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.050s 471.905us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 7.360s 2080.585us 5 5 100.00
rom_ctrl_csr_aliasing 5.710s 171.327us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.530s 233.658us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.780s 169.393us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 6.140s 178.010us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 27.200s 5612.948us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 13.450s 299.743us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 9.260s 2019.705us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 12.700s 190.724us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 12.700s 190.724us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 5.810s 172.206us 1 1 100.00
rom_ctrl_csr_rw 7.360s 2080.585us 5 5 100.00
rom_ctrl_csr_aliasing 5.710s 171.327us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.120s 530.918us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 5.810s 172.206us 1 1 100.00
rom_ctrl_csr_rw 7.360s 2080.585us 5 5 100.00
rom_ctrl_csr_aliasing 5.710s 171.327us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.120s 530.918us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 127.110s 36064.657us 16 20 80.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 31.300s 3143.267us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 284.620s 999.154us 5 5 100.00
rom_ctrl_tl_intg_err 85.380s 482.041us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 284.620s 999.154us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 284.620s 999.154us 5 5 100.00
sec_cm_checker_ctr_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 127.110s 36064.657us 16 20 80.00
sec_cm_checker_ctrl_flow_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 127.110s 36064.657us 16 20 80.00
sec_cm_checker_fsm_local_esc 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 127.110s 36064.657us 16 20 80.00
sec_cm_compare_ctrl_flow_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 127.110s 36064.657us 16 20 80.00
sec_cm_compare_ctr_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 127.110s 36064.657us 16 20 80.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 284.620s 999.154us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 284.620s 999.154us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 5.140s 319.454us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 5.140s 319.454us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 5.140s 319.454us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 85.380s 482.041us 25 25 100.00
sec_cm_bus_local_esc 18 22 81.82
rom_ctrl_corrupt_sig_fatal_chk 127.110s 36064.657us 16 20 80.00
rom_ctrl_kmac_err_chk 13.450s 299.743us 2 2 100.00
sec_cm_mux_mubi 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 127.110s 36064.657us 16 20 80.00
sec_cm_mux_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 127.110s 36064.657us 16 20 80.00
sec_cm_ctrl_redun 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 127.110s 36064.657us 16 20 80.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 31.300s 3143.267us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 284.620s 999.154us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 392.710s 4287.012us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 4 test runs
rom_ctrl_corrupt_sig_fatal_chk 25496999073917280931499780032273033154591254306363195385582740025830848146723 97
UVM_INFO @ 1615027294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 15364487092552803729544453411327242999052024701697048145908017048898407812225 93
UVM_INFO @ 1059891756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 106995444145759531517707480226714493259424116358836265197281336163071235119639 92
UVM_INFO @ 3549237914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 98293450904222707507894235593533396570135094327222353328375128442639450649610 92
UVM_INFO @ 3156445872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---