| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 16.720s | 1050.008us | 2 | 2 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 14.130s | 752.635us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| rom_ctrl_csr_rw | 12.740s | 286.681us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rom_ctrl_csr_bit_bash | 8.870s | 293.082us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rom_ctrl_csr_aliasing | 9.300s | 212.606us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| rom_ctrl_csr_mem_rw_with_rand_reset | 13.490s | 297.319us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| rom_ctrl_csr_rw | 12.740s | 286.681us | 5 | 5 | 100.00 | |
| rom_ctrl_csr_aliasing | 9.300s | 212.606us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| rom_ctrl_mem_walk | 7.000s | 3125.769us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| rom_ctrl_mem_partial_access | 6.050s | 698.520us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_throughput_chk | 2 | 2 | 100.00 | |||
| rom_ctrl_max_throughput_chk | 14.950s | 1061.367us | 2 | 2 | 100.00 | |
| stress_all | 20 | 20 | 100.00 | |||
| rom_ctrl_stress_all | 54.540s | 56510.803us | 20 | 20 | 100.00 | |
| kmac_err_chk | 2 | 2 | 100.00 | |||
| rom_ctrl_kmac_err_chk | 23.440s | 1423.767us | 2 | 2 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| rom_ctrl_alert_test | 11.970s | 1068.690us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| rom_ctrl_tl_errors | 20.400s | 1022.013us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| rom_ctrl_tl_errors | 20.400s | 1022.013us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 14.130s | 752.635us | 1 | 1 | 100.00 | |
| rom_ctrl_csr_rw | 12.740s | 286.681us | 5 | 5 | 100.00 | |
| rom_ctrl_csr_aliasing | 9.300s | 212.606us | 1 | 1 | 100.00 | |
| rom_ctrl_same_csr_outstanding | 15.220s | 1456.260us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 14.130s | 752.635us | 1 | 1 | 100.00 | |
| rom_ctrl_csr_rw | 12.740s | 286.681us | 5 | 5 | 100.00 | |
| rom_ctrl_csr_aliasing | 9.300s | 212.606us | 1 | 1 | 100.00 | |
| rom_ctrl_same_csr_outstanding | 15.220s | 1456.260us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| corrupt_sig_fatal_chk | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 277.970s | 8528.917us | 20 | 20 | 100.00 | |
| passthru_mem_tl_intg_err | 5 | 5 | 100.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 58.540s | 11445.652us | 5 | 5 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| rom_ctrl_sec_cm | 672.640s | 1395.983us | 5 | 5 | 100.00 | |
| rom_ctrl_tl_intg_err | 169.940s | 1345.940us | 25 | 25 | 100.00 | |
| prim_fsm_check | 5 | 5 | 100.00 | |||
| rom_ctrl_sec_cm | 672.640s | 1395.983us | 5 | 5 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| rom_ctrl_sec_cm | 672.640s | 1395.983us | 5 | 5 | 100.00 | |
| sec_cm_checker_ctr_consistency | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 277.970s | 8528.917us | 20 | 20 | 100.00 | |
| sec_cm_checker_ctrl_flow_consistency | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 277.970s | 8528.917us | 20 | 20 | 100.00 | |
| sec_cm_checker_fsm_local_esc | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 277.970s | 8528.917us | 20 | 20 | 100.00 | |
| sec_cm_compare_ctrl_flow_consistency | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 277.970s | 8528.917us | 20 | 20 | 100.00 | |
| sec_cm_compare_ctr_consistency | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 277.970s | 8528.917us | 20 | 20 | 100.00 | |
| sec_cm_compare_ctr_redun | 5 | 5 | 100.00 | |||
| rom_ctrl_sec_cm | 672.640s | 1395.983us | 5 | 5 | 100.00 | |
| sec_cm_fsm_sparse | 5 | 5 | 100.00 | |||
| rom_ctrl_sec_cm | 672.640s | 1395.983us | 5 | 5 | 100.00 | |
| sec_cm_mem_scramble | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 16.720s | 1050.008us | 2 | 2 | 100.00 | |
| sec_cm_mem_digest | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 16.720s | 1050.008us | 2 | 2 | 100.00 | |
| sec_cm_intersig_mubi | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 16.720s | 1050.008us | 2 | 2 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| rom_ctrl_tl_intg_err | 169.940s | 1345.940us | 25 | 25 | 100.00 | |
| sec_cm_bus_local_esc | 22 | 22 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 277.970s | 8528.917us | 20 | 20 | 100.00 | |
| rom_ctrl_kmac_err_chk | 23.440s | 1423.767us | 2 | 2 | 100.00 | |
| sec_cm_mux_mubi | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 277.970s | 8528.917us | 20 | 20 | 100.00 | |
| sec_cm_mux_consistency | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 277.970s | 8528.917us | 20 | 20 | 100.00 | |
| sec_cm_ctrl_redun | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 277.970s | 8528.917us | 20 | 20 | 100.00 | |
| sec_cm_ctrl_mem_integrity | 5 | 5 | 100.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 58.540s | 11445.652us | 5 | 5 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| rom_ctrl_sec_cm | 672.640s | 1395.983us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 20 | 20 | 100.00 | |||
| rom_ctrl_stress_all_with_rand_reset | 343.040s | 4116.416us | 20 | 20 | 100.00 | |