| V1 |
|
100.00% |
| V2 |
|
84.25% |
| V2S |
|
100.00% |
| V3 |
|
45.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 2.380s | 413.145us | 20 | 20 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.940s | 28.576us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| rv_timer_csr_rw | 0.910s | 14.592us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_timer_csr_bit_bash | 2.780s | 124.166us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rv_timer_csr_aliasing | 1.010s | 18.020us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.930s | 142.215us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| rv_timer_csr_rw | 0.910s | 14.592us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.010s | 18.020us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 0 | 20 | 0.00 | |||
| rv_timer_random_reset | 11.850s | 30429.967us | 0 | 20 | 0.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 4.580s | 4660.280us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 293.570s | 195875.171us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 293.570s | 195875.171us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 8.960s | 10550.674us | 20 | 20 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| rv_timer_alert_test | 0.870s | 11.378us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| rv_timer_intr_test | 0.870s | 20.321us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| rv_timer_tl_errors | 3.090s | 168.433us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| rv_timer_tl_errors | 3.090s | 168.433us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.940s | 28.576us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.910s | 14.592us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.010s | 18.020us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.060s | 21.296us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.940s | 28.576us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.910s | 14.592us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.010s | 18.020us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.060s | 21.296us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| rv_timer_sec_cm | 1.200s | 148.267us | 5 | 5 | 100.00 | |
| rv_timer_tl_intg_err | 1.730s | 562.894us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| rv_timer_tl_intg_err | 1.730s | 562.894us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 5 | 10 | 50.00 | |||
| rv_timer_min | 1.260s | 289.041us | 5 | 10 | 50.00 | |
| max_value | 2 | 10 | 20.00 | |||
| rv_timer_max | 1.540s | 175.509us | 2 | 10 | 20.00 | |
| stress_all_with_rand_reset | 11 | 20 | 55.00 | |||
| rv_timer_stress_all_with_rand_reset | 54.640s | 14033.776us | 11 | 20 | 55.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | 25 test runs | |||
| rv_timer_min | 97632869404402120136483570716470300788035267257574285356300232899727445539702 | 75 |
UVM_INFO @ 220623611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 31789444344089827716939283429449717947644476549876178822344445776941531341856 | 75 |
UVM_INFO @ 81210807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 59868515315907841123012363664545341046508435931930171516794753786225392101329 | 77 |
UVM_INFO @ 837518304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 63320260963327612947447358949613861132168344332853667025652149661521049201676 | 78 |
UVM_INFO @ 930431489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 105239109578569158271196341175053588051371377058377989554531335218969280807632 | 75 |
UVM_INFO @ 107246661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 88869719771275811759665028217480292546582909602872930779411521077426632416631 | 75 |
UVM_INFO @ 63382224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 28908179630920060728666380019052815931779956336427784720579868868951206522563 | 75 |
UVM_INFO @ 314444876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 32358123083325694422368222621665230910656289520136246572395625144921041801095 | 76 |
UVM_INFO @ 153483885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 35878293839924950015296024918814591117336347402379372261254353909568279040278 | 75 |
UVM_INFO @ 150386712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 84740553855889961394391282267534143844022466289533904992968805233819125797607 | 75 |
UVM_INFO @ 289041451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 85561667774856489509056165131335686483906303956302404270656505063375252375093 | 75 |
UVM_INFO @ 357989360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 3227948650170092632804625007127327656370923067358710772703435606597486725138 | 75 |
UVM_INFO @ 224342591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 72482524265413627123921648626244586214781156088769061099308325072605783404611 | 76 |
UVM_INFO @ 80690565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 73132870784449579756891886232054729558131185580021087919750825915683321642270 | 75 |
UVM_INFO @ 111988517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 27095512843802572066347066838775692743457330970837914589384496222683303600787 | 76 |
UVM_INFO @ 504523355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 39273572894389856696185236618585118056032683218848392809240428738736994733270 | 75 |
UVM_INFO @ 843335502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 115281991348396886295014891149708850598716354487462620514672526903072046808964 | 75 |
UVM_INFO @ 143108584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 44862847087096169919290717919975599637789915150364907353449470795891569209648 | 75 |
UVM_INFO @ 125959101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 55101030769767312848664579713820880087383453513833099148885385351384211928413 | 75 |
UVM_INFO @ 603659892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 13137366552952254173341890537315072582243843715902574183249637448029609226641 | 75 |
UVM_INFO @ 1361178696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 2038592205239893660777014871111164977794349326725776637266373682401262623468 | 75 |
UVM_INFO @ 496130533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 54324418484870589403637494250631797838142943129750056199814461392916074921066 | 76 |
UVM_INFO @ 96059465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 92200095924566551134788099763583163923983914770687524465804859469374453062013 | 75 |
UVM_INFO @ 253769442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 66317357877140473313742432860216656933368971311489477959328974450698865320209 | 75 |
UVM_INFO @ 30429966892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 4103179441395625827696482046095040728426637685845271420155149518151093504120 | 75 |
UVM_INFO @ 537409875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 8 test runs | |||
| rv_timer_max | 70341817739414335966018785395988447826218900217009908957705301413011190276566 | 75 |
UVM_INFO @ 180002831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 106881786493919930670689308141302007943003827687709062322000712032100297564607 | 75 |
UVM_INFO @ 91308663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 50045735744165208915304858155309815505745530203562268387135865441396422145212 | 77 |
UVM_INFO @ 186848131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 27413024638215513128945242013692513072967888733026420025660688144082619883452 | 75 |
UVM_INFO @ 506363631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 101805232344026069730796529954619513309098422789972141772713694112125766451199 | 75 |
UVM_INFO @ 175508590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 100505771758450997320685366620805237540509025266990068236404487719353321945009 | 75 |
UVM_INFO @ 126269474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 70795852392711056781949843083780450861793342183329093570748388210392248581528 | 75 |
UVM_INFO @ 101639354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 15390963307165977127875675304230704382033836678299578645438573917048506863391 | 75 |
UVM_INFO @ 84941521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) | 5 test runs | |||
| rv_timer_stress_all_with_rand_reset | 108761173306350847509856361505886273987808400096612249835590788222920619372458 | 251 |
UVM_INFO @ 10551442203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 81233141886755518148652325467775143258289805545940887019797941381773432725787 | 468 |
UVM_INFO @ 15254333499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 73527076873271997909107930775256957814718054951743236763998358397220694589330 | 267 |
UVM_INFO @ 10831034862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 80146353113317961253930846913149966376485068476096113865904093379611606994969 | 169 |
UVM_INFO @ 3158046539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 37699072431220484552770097802782031416573019763945893848684108001869112708370 | 106 |
UVM_INFO @ 1424443352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | 4 test runs | |||
| rv_timer_stress_all_with_rand_reset | 7104010614899528401754655624761944164602720066206626409791376865088565493100 | 326 |
UVM_INFO @ 18779953203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 32807779401184719505153905528960856944126168742899933869572737429097700369987 | 225 |
UVM_INFO @ 1486899931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 58085341587323027702860366689691987273905686262136486846372052923285815264333 | 250 |
UVM_INFO @ 17767820463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 48085196373731805496313669843191414703748031571547032701997040712887117406415 | 157 |
UVM_INFO @ 3642153285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|