Simulation Results: spi_device/2p

 
06/06/2026 15:22:54 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.25 %
  • code
  • 94.21 %
  • assert
  • 95.49 %
  • func
  • 99.06 %
  • line
  • 98.96 %
  • branch
  • 98.39 %
  • cond
  • 96.61 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
99.74%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 25 25 100.00
spi_device_flash_and_tpm 397.410s 87795.489us 25 25 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.610s 138.263us 1 1 100.00
csr_rw 5 5 100.00
spi_device_csr_rw 2.680s 434.532us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 31.550s 1065.194us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 16.520s 736.740us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_device_csr_mem_rw_with_rand_reset 3.700s 652.110us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_device_csr_rw 2.680s 434.532us 5 5 100.00
spi_device_csr_aliasing 16.520s 736.740us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 1.020s 36.734us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.630s 45.015us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 15 15 100.00
spi_device_csb_read 1.180s 77.309us 15 15 100.00
mem_parity 20 20 100.00
spi_device_mem_parity 1.480s 128.159us 20 20 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 1.070s 37.149us 1 1 100.00
tpm_read 15 15 100.00
spi_device_tpm_rw 2.930s 673.464us 15 15 100.00
tpm_write 15 15 100.00
spi_device_tpm_rw 2.930s 673.464us 15 15 100.00
tpm_hw_reg 30 30 100.00
spi_device_tpm_read_hw_reg 22.670s 6273.489us 15 15 100.00
spi_device_tpm_sts_read 1.370s 80.248us 15 15 100.00
tpm_fully_random_case 15 15 100.00
spi_device_tpm_all 36.760s 23741.917us 15 15 100.00
pass_cmd_filtering 40 40 100.00
spi_device_pass_cmd_filtering 20.820s 19499.545us 15 15 100.00
spi_device_flash_all 242.220s 41186.441us 25 25 100.00
pass_addr_translation 40 40 100.00
spi_device_pass_addr_payload_swap 44.030s 25691.094us 15 15 100.00
spi_device_flash_all 242.220s 41186.441us 25 25 100.00
pass_payload_translation 40 40 100.00
spi_device_pass_addr_payload_swap 44.030s 25691.094us 15 15 100.00
spi_device_flash_all 242.220s 41186.441us 25 25 100.00
cmd_info_slots 25 25 100.00
spi_device_flash_all 242.220s 41186.441us 25 25 100.00
cmd_read_status 40 40 100.00
spi_device_intercept 23.030s 2975.464us 15 15 100.00
spi_device_flash_all 242.220s 41186.441us 25 25 100.00
cmd_read_jedec 40 40 100.00
spi_device_intercept 23.030s 2975.464us 15 15 100.00
spi_device_flash_all 242.220s 41186.441us 25 25 100.00
cmd_read_sfdp 40 40 100.00
spi_device_intercept 23.030s 2975.464us 15 15 100.00
spi_device_flash_all 242.220s 41186.441us 25 25 100.00
cmd_fast_read 40 40 100.00
spi_device_intercept 23.030s 2975.464us 15 15 100.00
spi_device_flash_all 242.220s 41186.441us 25 25 100.00
cmd_read_pipeline 40 40 100.00
spi_device_intercept 23.030s 2975.464us 15 15 100.00
spi_device_flash_all 242.220s 41186.441us 25 25 100.00
flash_cmd_upload 15 15 100.00
spi_device_upload 29.500s 8190.609us 15 15 100.00
mailbox_command 15 15 100.00
spi_device_mailbox 75.100s 12243.173us 15 15 100.00
mailbox_cross_outside_command 15 15 100.00
spi_device_mailbox 75.100s 12243.173us 15 15 100.00
mailbox_cross_inside_command 15 15 100.00
spi_device_mailbox 75.100s 12243.173us 15 15 100.00
cmd_read_buffer 30 30 100.00
spi_device_flash_mode 57.880s 62388.409us 15 15 100.00
spi_device_read_buffer_direct 19.290s 3502.268us 15 15 100.00
cmd_dummy_cycle 40 40 100.00
spi_device_mailbox 75.100s 12243.173us 15 15 100.00
spi_device_flash_all 242.220s 41186.441us 25 25 100.00
quad_spi 25 25 100.00
spi_device_flash_all 242.220s 41186.441us 25 25 100.00
dual_spi 25 25 100.00
spi_device_flash_all 242.220s 41186.441us 25 25 100.00
4b_3b_feature 15 15 100.00
spi_device_cfg_cmd 6.680s 823.881us 15 15 100.00
write_enable_disable 15 15 100.00
spi_device_cfg_cmd 6.680s 823.881us 15 15 100.00
flash_mode_ignore_cmds 15 15 100.00
spi_device_flash_mode_ignore_cmds 199.650s 35448.562us 15 15 100.00
TPM_with_flash_or_passthrough_mode 25 25 100.00
spi_device_flash_and_tpm 397.410s 87795.489us 25 25 100.00
tpm_and_flash_trans_with_min_inactive_time 25 25 100.00
spi_device_flash_and_tpm_min_idle 295.970s 182005.709us 25 25 100.00
stress_all 14 15 93.33
spi_device_stress_all 1072.380s 950160.190us 14 15 93.33
alert_test 10 10 100.00
spi_device_alert_test 1.080s 44.228us 10 10 100.00
intr_test 10 10 100.00
spi_device_intr_test 1.160s 187.201us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_device_tl_errors 6.220s 235.777us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_device_tl_errors 6.220s 235.777us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_device_csr_hw_reset 1.610s 138.263us 1 1 100.00
spi_device_csr_rw 2.680s 434.532us 5 5 100.00
spi_device_csr_aliasing 16.520s 736.740us 1 1 100.00
spi_device_same_csr_outstanding 4.750s 994.961us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_device_csr_hw_reset 1.610s 138.263us 1 1 100.00
spi_device_csr_rw 2.680s 434.532us 5 5 100.00
spi_device_csr_aliasing 16.520s 736.740us 1 1 100.00
spi_device_same_csr_outstanding 4.750s 994.961us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_device_sec_cm 1.700s 115.818us 5 5 100.00
spi_device_tl_intg_err 21.990s 1907.021us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
spi_device_tl_intg_err 21.990s 1907.021us 25 25 100.00

Error Messages

   Test seed line log context
UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) CSR last_read_addr compare mismatch act * != exp * 1 test run
spi_device_stress_all 80674161062058307133500922821108818182456703225672430036042553253751281728010 220
tl_ul_fuzzy_flash_status_q[i] = 0xfe02f2
tl_ul_fuzzy_flash_status_q[i] = 0x97c86
tl_ul_fuzzy_flash_status_q[i] = 0x477eba
tl_ul_fuzzy_flash_status_q[i] = 0xc77d1e