Simulation Results: spi_host

 
06/06/2026 15:22:54 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.20 %
  • code
  • 95.06 %
  • assert
  • 96.78 %
  • func
  • 90.76 %
  • block
  • 97.00 %
  • line
  • 98.76 %
  • branch
  • 93.45 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.45%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 66.000s 5478.267us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 30.967us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 2.000s 38.419us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 43.677us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 96.976us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 80.875us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 2.000s 38.419us 5 5 100.00
spi_host_csr_aliasing 2.000s 96.976us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 23.751us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 17.787us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 182.976us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 24.000s 1015.090us 10 10 100.00
spi_host_error_cmd 2.000s 64.531us 10 10 100.00
spi_host_event 202.000s 26842.881us 10 10 100.00
clock_rate 10 10 100.00
spi_host_speed 5.000s 194.069us 10 10 100.00
speed 10 10 100.00
spi_host_speed 5.000s 194.069us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 5.000s 194.069us 10 10 100.00
upper_range_clkdiv 5 5 100.00
spi_host_upper_range_clkdiv 219.000s 4839.245us 5 5 100.00
sw_reset 10 10 100.00
spi_host_sw_reset 18.000s 1703.976us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 48.814us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 5.000s 194.069us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 5.000s 194.069us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 66.000s 5478.267us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 66.000s 5478.267us 10 10 100.00
stress_all 9 10 90.00
spi_host_stress_all 528.000s 1000000.000us 9 10 90.00
spien 10 10 100.00
spi_host_spien 22.000s 970.702us 10 10 100.00
stall 10 10 100.00
spi_host_status_stall 59.000s 1548.414us 10 10 100.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 4.000s 664.969us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 24.000s 1015.090us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 2.000s 91.768us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 22.377us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 4.000s 121.797us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 4.000s 121.797us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 30.967us 1 1 100.00
spi_host_csr_rw 2.000s 38.419us 5 5 100.00
spi_host_csr_aliasing 2.000s 96.976us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 31.921us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 30.967us 1 1 100.00
spi_host_csr_rw 2.000s 38.419us 5 5 100.00
spi_host_csr_aliasing 2.000s 96.976us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 31.921us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 2.000s 129.719us 25 25 100.00
spi_host_sec_cm 2.000s 44.489us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 2.000s 129.719us 25 25 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
spi_host_stress_all 75195138997783582617976039718232231609573577950062941023099154780567885217782 185
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---