| V1 |
|
97.30% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 54.636us | 8 | 8 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 26.558us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 24.216us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_bit_bash | 2.000s | 149.015us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_aliasing | 2.000s | 26.850us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 4 | 5 | 80.00 | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 3.000s | 95.598us | 4 | 5 | 80.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 24.216us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 26.850us | 1 | 1 | 100.00 | |
| mem_walk | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_walk | 12.000s | 1291.701us | 8 | 8 | 100.00 | |
| mem_partial_access | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_partial_access | 8.000s | 1493.103us | 8 | 8 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| multiple_keys | 8 | 8 | 100.00 | |||
| sram_ctrl_multiple_keys | 16.000s | 2991.451us | 8 | 8 | 100.00 | |
| stress_pipeline | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_pipeline | 240.000s | 33476.711us | 8 | 8 | 100.00 | |
| bijection | 8 | 8 | 100.00 | |||
| sram_ctrl_bijection | 11.000s | 10301.615us | 8 | 8 | 100.00 | |
| access_during_key_req | 8 | 8 | 100.00 | |||
| sram_ctrl_access_during_key_req | 21.000s | 1205.689us | 8 | 8 | 100.00 | |
| lc_escalation | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 12.000s | 3103.500us | 8 | 8 | 100.00 | |
| executable | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 12.000s | 1689.699us | 8 | 8 | 100.00 | |
| partial_access | 16 | 16 | 100.00 | |||
| sram_ctrl_partial_access | 3.000s | 181.830us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access_b2b | 428.000s | 112030.824us | 8 | 8 | 100.00 | |
| max_throughput | 24 | 24 | 100.00 | |||
| sram_ctrl_max_throughput | 2.000s | 429.982us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_partial_write | 2.000s | 143.550us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_readback | 2.000s | 77.589us | 8 | 8 | 100.00 | |
| regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 11.000s | 1889.302us | 8 | 8 | 100.00 | |
| ram_cfg | 8 | 8 | 100.00 | |||
| sram_ctrl_ram_cfg | 2.000s | 167.080us | 8 | 8 | 100.00 | |
| stress_all | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all | 46.000s | 13340.812us | 8 | 8 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| sram_ctrl_alert_test | 2.000s | 12.963us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 6.000s | 145.804us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 6.000s | 145.804us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 26.558us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 24.216us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 26.850us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 24.950us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 26.558us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 24.216us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 26.850us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 24.950us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| passthru_mem_tl_intg_err | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 5.000s | 428.374us | 5 | 5 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| sram_ctrl_sec_cm | 8.000s | 7110.453us | 5 | 5 | 100.00 | |
| sram_ctrl_tl_intg_err | 4.000s | 2403.864us | 25 | 25 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 8.000s | 7110.453us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_intg_err | 4.000s | 2403.864us | 25 | 25 | 100.00 | |
| sec_cm_ctrl_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 11.000s | 1889.302us | 8 | 8 | 100.00 | |
| sec_cm_readback_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 11.000s | 1889.302us | 8 | 8 | 100.00 | |
| sec_cm_exec_config_regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 24.216us | 5 | 5 | 100.00 | |
| sec_cm_exec_config_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 12.000s | 1689.699us | 8 | 8 | 100.00 | |
| sec_cm_exec_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 12.000s | 1689.699us | 8 | 8 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 12.000s | 1689.699us | 8 | 8 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 12.000s | 3103.500us | 8 | 8 | 100.00 | |
| sec_cm_prim_ram_ctrl_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_mubi_enc_err | 2.000s | 521.850us | 8 | 8 | 100.00 | |
| sec_cm_mem_integrity | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 5.000s | 428.374us | 5 | 5 | 100.00 | |
| sec_cm_mem_readback | 8 | 8 | 100.00 | |||
| sram_ctrl_readback_err | 2.000s | 38.630us | 8 | 8 | 100.00 | |
| sec_cm_mem_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 54.636us | 8 | 8 | 100.00 | |
| sec_cm_addr_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 54.636us | 8 | 8 | 100.00 | |
| sec_cm_instr_bus_lc_gated | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 12.000s | 1689.699us | 8 | 8 | 100.00 | |
| sec_cm_ram_tl_lc_gate_fsm_sparse | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 8.000s | 7110.453us | 5 | 5 | 100.00 | |
| sec_cm_key_global_esc | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 12.000s | 3103.500us | 8 | 8 | 100.00 | |
| sec_cm_key_local_esc | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 8.000s | 7110.453us | 5 | 5 | 100.00 | |
| sec_cm_init_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 8.000s | 7110.453us | 5 | 5 | 100.00 | |
| sec_cm_scramble_key_sideload | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 54.636us | 8 | 8 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 8.000s | 7110.453us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all_with_rand_reset | 48.000s | 8288.070us | 8 | 8 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * | 1 test run | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 58649200968908845705585134900125579716550108511612932222633235753088646472030 | 94 |
UVM_INFO @ 121952703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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