Simulation Results: sysrst_ctrl

 
06/06/2026 15:22:54 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.20 %
  • code
  • 98.25 %
  • assert
  • 98.75 %
  • func
  • 91.60 %
  • line
  • 99.37 %
  • branch
  • 99.41 %
  • cond
  • 97.60 %
  • toggle
  • 100.00 %
  • FSM
  • 94.87 %
Validation stages
V1
100.00%
V2
98.80%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
sysrst_ctrl_smoke 6.420s 2112.060us 10 10 100.00
input_output_inverted 10 10 100.00
sysrst_ctrl_in_out_inverted 8.850s 2458.741us 10 10 100.00
combo_detect_ec_rst 5 5 100.00
sysrst_ctrl_combo_detect_ec_rst 9.740s 2152.881us 5 5 100.00
combo_detect_ec_rst_with_pre_cond 5 5 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 8.090s 2302.302us 5 5 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 2.120s 4069.031us 1 1 100.00
csr_rw 5 5 100.00
sysrst_ctrl_csr_rw 9.000s 2037.279us 5 5 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 48.300s 38940.219us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 4.550s 3550.440us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 3.130s 2059.506us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sysrst_ctrl_csr_rw 9.000s 2037.279us 5 5 100.00
sysrst_ctrl_csr_aliasing 4.550s 3550.440us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 25 25 100.00
sysrst_ctrl_combo_detect 393.680s 150515.559us 25 25 100.00
combo_detect_with_pre_cond 97 100 97.00
sysrst_ctrl_combo_detect_with_pre_cond 568.700s 259595.479us 97 100 97.00
auto_block_key_outputs 25 25 100.00
sysrst_ctrl_auto_blk_key_output 656.850s 283692.190us 25 25 100.00
keyboard_input_triggered_interrupt 50 50 100.00
sysrst_ctrl_edge_detect 1297.760s 551364.142us 50 50 100.00
pin_output_keyboard_inversion_control 10 10 100.00
sysrst_ctrl_pin_override_test 9.750s 2512.513us 10 10 100.00
pin_input_value_accessibility 10 10 100.00
sysrst_ctrl_pin_access_test 7.890s 2022.980us 10 10 100.00
ec_power_on_reset 10 10 100.00
sysrst_ctrl_ec_pwr_on_rst 15.820s 4337.827us 10 10 100.00
flash_write_protect_output 10 10 100.00
sysrst_ctrl_flash_wr_prot_out 10.720s 2612.295us 10 10 100.00
ultra_low_power_test 24 25 96.00
sysrst_ctrl_ultra_low_pwr 277.690s 1268618.155us 24 25 96.00
sysrst_ctrl_feature_disable 2 2 100.00
sysrst_ctrl_feature_disable 46.940s 37454.762us 2 2 100.00
stress_all 10 10 100.00
sysrst_ctrl_stress_all 235.290s 101722.218us 10 10 100.00
alert_test 10 10 100.00
sysrst_ctrl_alert_test 8.350s 2012.068us 10 10 100.00
intr_test 10 10 100.00
sysrst_ctrl_intr_test 7.900s 2016.170us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sysrst_ctrl_tl_errors 10.720s 2053.303us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sysrst_ctrl_tl_errors 10.720s 2053.303us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sysrst_ctrl_csr_hw_reset 2.120s 4069.031us 1 1 100.00
sysrst_ctrl_csr_rw 9.000s 2037.279us 5 5 100.00
sysrst_ctrl_csr_aliasing 4.550s 3550.440us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 19.560s 10434.155us 5 5 100.00
tl_d_partial_access 12 12 100.00
sysrst_ctrl_csr_hw_reset 2.120s 4069.031us 1 1 100.00
sysrst_ctrl_csr_rw 9.000s 2037.279us 5 5 100.00
sysrst_ctrl_csr_aliasing 4.550s 3550.440us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 19.560s 10434.155us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
sysrst_ctrl_sec_cm 62.350s 22014.116us 5 5 100.00
sysrst_ctrl_tl_intg_err 128.720s 42454.529us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
sysrst_ctrl_tl_intg_err 128.720s 42454.529us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
sysrst_ctrl_stress_all_with_rand_reset 20.860s 5610.723us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)  1 test run
sysrst_ctrl_ultra_low_pwr 5342325294944943799120280058113058029306084469100756074916543892290451340881 655
UVM_ERROR @ 5591886221 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 5591886221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(9) vs exp(4) +/-* 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 100192755403909255295287624419650574433740203495291473230900222180135262125491 665
UVM_ERROR @ 15735688447 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(9) vs exp(4) +/-4
UVM_INFO @ 15735688447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-* 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 104936288767089250218488663013829250303880036491932374002982629159937060406996 663
UVM_ERROR @ 13581858907 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(6) vs exp(2) +/-4
UVM_INFO @ 13581858907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 7281427097716214347359037973368980626301442546432016941152841528847080348256 688
UVM_INFO @ 38710905099 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 38730905099 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 48796348079 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2f
UVM_INFO @ 48796369131 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x20