Simulation Results

Simulation Results: adc_ctrl

13/06/2026 02:15:06 DVSim: v1.49.0 sha: 9424e63 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
67.53 %

code
96.19 %

assert
92.71 %

func
13.69 %

line
98.89 %

branch
97.46 %

cond
87.55 %

toggle
99.76 %

FSM
97.30 %

Validation stages

V1		100.00%
V2		49.72%
V2S		100.00%
V3		10.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	adc_ctrl_smoke	15.050s	5970.823us	10	10	100.00
csr_hw_reset				1	1	100.00
	adc_ctrl_csr_hw_reset	1.700s	994.902us	1	1	100.00
csr_rw				5	5	100.00
	adc_ctrl_csr_rw	2.550s	527.302us	5	5	100.00
csr_bit_bash				1	1	100.00
	adc_ctrl_csr_bit_bash	3.920s	1371.357us	1	1	100.00
csr_aliasing				1	1	100.00
	adc_ctrl_csr_aliasing	4.440s	1323.398us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	adc_ctrl_csr_mem_rw_with_rand_reset	2.550s	516.220us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	adc_ctrl_csr_rw	2.550s	527.302us	5	5	100.00
	adc_ctrl_csr_aliasing	4.440s	1323.398us	1	1	100.00

88/177 passed

49.72 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
filters_polled				0	10	0.00
	adc_ctrl_filters_polled	2.050s	428.858us	0	10	0.00
filters_polled_fixed				0	10	0.00
	adc_ctrl_filters_polled_fixed	2.080s	518.979us	0	10	0.00
filters_interrupt				0	10	0.00
	adc_ctrl_filters_interrupt	2.070s	489.608us	0	10	0.00
filters_interrupt_fixed				0	10	0.00
	adc_ctrl_filters_interrupt_fixed	2.110s	456.442us	0	10	0.00
filters_wakeup				0	10	0.00
	adc_ctrl_filters_wakeup	2.000s	462.900us	0	10	0.00
filters_wakeup_fixed				0	10	0.00
	adc_ctrl_filters_wakeup_fixed	2.110s	506.954us	0	10	0.00
filters_both				0	10	0.00
	adc_ctrl_filters_both	1.800s	399.349us	0	10	0.00
clock_gating				0	10	0.00
	adc_ctrl_clock_gating	1.920s	418.333us	0	10	0.00
poweron_counter				10	10	100.00
	adc_ctrl_poweron_counter	12.100s	4666.420us	10	10	100.00
lowpower_counter				10	10	100.00
	adc_ctrl_lowpower_counter	63.760s	37157.617us	10	10	100.00
fsm_reset				10	10	100.00
	adc_ctrl_fsm_reset	225.820s	121738.684us	10	10	100.00
stress_all				1	10	10.00
	adc_ctrl_stress_all	225.810s	120670.140us	1	10	10.00
alert_test				10	10	100.00
	adc_ctrl_alert_test	2.070s	468.976us	10	10	100.00
intr_test				10	10	100.00
	adc_ctrl_intr_test	2.220s	526.430us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	adc_ctrl_tl_errors	4.510s	665.551us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	adc_ctrl_tl_errors	4.510s	665.551us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	adc_ctrl_csr_hw_reset	1.700s	994.902us	1	1	100.00
	adc_ctrl_csr_rw	2.550s	527.302us	5	5	100.00
	adc_ctrl_csr_aliasing	4.440s	1323.398us	1	1	100.00
	adc_ctrl_same_csr_outstanding	11.780s	5422.060us	5	5	100.00
tl_d_partial_access				12	12	100.00
	adc_ctrl_csr_hw_reset	1.700s	994.902us	1	1	100.00
	adc_ctrl_csr_rw	2.550s	527.302us	5	5	100.00
	adc_ctrl_csr_aliasing	4.440s	1323.398us	1	1	100.00
	adc_ctrl_same_csr_outstanding	11.780s	5422.060us	5	5	100.00

V2S

30/30 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	adc_ctrl_sec_cm	17.810s	7834.399us	5	5	100.00
	adc_ctrl_tl_intg_err	24.850s	8412.935us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	adc_ctrl_tl_intg_err	24.850s	8412.935us	25	25	100.00

1/10 passed

10.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	10	10.00
	adc_ctrl_stress_all_with_rand_reset	8.620s	2630.659us	1	10	10.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [, ]				98 test runs
	adc_ctrl_filters_polled	27329295549720379521213753380039031682253454553864944257184790702999331956185	386	UVM_INFO @ 371641634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	12774030551298558268738391167185455324459253974139144879878550427931681732928	386	UVM_INFO @ 325259251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	75223527417826116158168363606284944448141211819633598171794430091931278572640	386	UVM_INFO @ 487411984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	93376868797978909571383900450595751677554023332395183447137595782191646483605	386	UVM_INFO @ 395841301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	97971722668106458549264458400474337418568827171525646903457045782358242500411	386	UVM_INFO @ 404704758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	25527680681119043042620283248221879317613513425584194097334816185070906390362	386	UVM_INFO @ 280684384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	8570357257546018958182704749513363600061467616835431751077909930953801831054	386	UVM_INFO @ 325072327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	102693078117522329407565141119651495781339023648424637563671592485162240317786	386	UVM_INFO @ 307737666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	84020919936793828724716688831868195339032867576608145485798798274126488329936	417	UVM_INFO @ 2389668525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	46808923950285779750016004800612514014261369109698959890354114540124778635163	387	UVM_INFO @ 825669580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	82390729967234605836377922990681930323753144806012155129575187987532011181478	386	UVM_INFO @ 428857872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	95636460800612066205989505891800258376602225212239419464446495326305346576285	386	UVM_INFO @ 496453736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	28096529031797439950536460364230533496708193999517024371048892462478228058934	386	UVM_INFO @ 482868771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	21583752548363595570663656822047116419628874314646985985633036568955430653255	386	UVM_INFO @ 316058099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	78900031411839614061741426432318669087397042582384806968316661434709558691238	386	UVM_INFO @ 452355345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	31645225595386906725967849982606942433415106508539753306666696627873963510765	386	UVM_INFO @ 504091717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	102491648358334297988038477796407233046962024014756252674346594967629137371950	386	UVM_INFO @ 365084805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	20714672120232186486856621868070822974238092831569204465704097131161770256124	386	UVM_INFO @ 286746451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	39559208473096998268189866015960888048651867130279555793942118125333909006156	392	UVM_INFO @ 802970005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	50404085304678751769694924297907296678154105125034193616179768870497202058099	414	UVM_INFO @ 123628686531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	112353360689323941660941856759816400463644565580759533828786768524868058523713	386	UVM_INFO @ 483853510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	737666997151650280530900174651385917217798291422967971817924369646494238754	386	UVM_INFO @ 289177578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	412260164687053573855372129496391561293039604350817323269962573346872431271	386	UVM_INFO @ 338746566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	72060050232668018666036816757070521160301466914529025570853618934384394205991	386	UVM_INFO @ 423226030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	23524721697762958686735789443976022261784067420161843654351085811725583959669	386	UVM_INFO @ 462900352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	76508772021104586709207941123601439820529341270533450976415349527512983839165	386	UVM_INFO @ 506954373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	56167079778206715549126371563129185952771866923353633477313060738714874747369	386	UVM_INFO @ 334133200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	54084707848385501495188838550979293779676225634486575054474383660757917661968	386	UVM_INFO @ 297724703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	45830848533705914950479506882210280211773024088321291831359855119081750230256	392	UVM_INFO @ 763852073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	60758089995870653261950387768762345988153752876920984866235074894831167596376	387	UVM_INFO @ 705897551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	10591296849764220264858580830495360327516487582583167326034467744537756990605	386	UVM_INFO @ 297586353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	34767058854526186647319622648880127577312288477750472233231477846703227200296	386	UVM_INFO @ 343186664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	18481809492891152457187153565679888329740661985109917190189687213642093306007	386	UVM_INFO @ 516457758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	107057203550560197191660876848951681893442028766862790659797905356675891056347	386	UVM_INFO @ 456442109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	45632967224403378638739459698472454957894457352949897987739964606250373204382	386	UVM_INFO @ 360786396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	105026711039603893507539243033259618896263831734336486545282889246667808555514	386	UVM_INFO @ 455853248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	101793983479751501703165424516355257463469996068111232383578114291426251458809	386	UVM_INFO @ 424799048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	21804726626378898665364935284443036379712335741271234334451977729293484722116	386	UVM_INFO @ 463233344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	35494080962044031356714137178552221475694294045861139599540995518117842801036	387	UVM_INFO @ 837807268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	77497530584996035688272765468364090280290730452952706167390798637546769421140	386	UVM_INFO @ 444758025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	107533806983408259735908796378388647526088480762061140136829465939232496151424	386	UVM_INFO @ 335408473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	51983746198663978523562349808269369120381793957182827932913618389537289600374	386	UVM_INFO @ 415136145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	83271931365413611271303192340001461225030653032102255124471644378489284104263	386	UVM_INFO @ 339800437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	101499426972295573794126739476489868662102879998850101395634789346667915518980	386	UVM_INFO @ 387237753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	88741816565414303035233955310857691099364975643997816914775247025871255504960	386	UVM_INFO @ 294940580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	60074610809131951611159192486657689528215506898573075364684201033028476136610	386	UVM_INFO @ 276859253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	89572939212630240774821143711970962745383999506449125432254144625430089452058	386	UVM_INFO @ 407692623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	37829608170981429265685669240786662524601860767758345115567014228467828861516	405	UVM_INFO @ 965418468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	72348894557627823358427087317620355627886540183470233347597388725004562629055	427	UVM_INFO @ 120670139564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	97387875168557067418659609514173482641865423103121185937995797472933668753435	386	UVM_INFO @ 299166434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	13770257906219359600378355608060614863962475832281838018043612280278349088039	386	UVM_INFO @ 422603688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	18538471818485585130906329055098118555873389809818597783280078526028133230347	386	UVM_INFO @ 489608444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	92995580029776653393698670891009973378672507694664804559483243757797681634689	386	UVM_INFO @ 391586986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	13113636433843208640144931642959087541833867959625886521158724351199887587574	386	UVM_INFO @ 439989925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	35924675697881015859703899378025063122186026059922166356798683792008459636782	386	UVM_INFO @ 317129436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	66228025541367989874251328854375722596571403436315830383836357756053539021494	386	UVM_INFO @ 332508497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	38836854511784839144731963969170077302858296899529161342526026329046952450319	386	UVM_INFO @ 393173335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	4260034873715586574064190122338378936603911581541075522078577442874731576082	392	UVM_INFO @ 722066624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	12723393063689459403351433687753382003323332422658876684371863347155091576370	387	UVM_INFO @ 840317967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	21835896923074436744923315798727263411095160779294997449263372006709762499125	386	UVM_INFO @ 386348491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	50234664429923613965207556830151243098684365158583698878623768757086508607550	386	UVM_INFO @ 385115609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	74013340454790847227608462539821243410644677711829152938151684061557625933877	386	UVM_INFO @ 325824114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	64006656459049418124676528646928164229839946495022738135172306590394126734169	386	UVM_INFO @ 402905684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	10619875413404099940097598708021915786049466681183963787661306456261939705583	386	UVM_INFO @ 493408881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	12650477402285085954251524311405853414677436390346599031900149090665097996305	386	UVM_INFO @ 332825553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	64316388501851989072577380266517274237774344026845432647063796578432195905814	386	UVM_INFO @ 418333494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	45134654190618574484923609014367269957594866021790576692848029566741846459398	386	UVM_INFO @ 500153586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	54248468806217921045191279030761372202871550671227182835874521163162164962154	392	UVM_INFO @ 983184722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	67779940209415598360758753487506908600865377129698563635072239396182885162446	387	UVM_INFO @ 676181258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	88243384050172895471675911521235887216026871697909301907744876561624658531334	386	UVM_INFO @ 315105324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	96585397266868632867363637907138374100281447504827909684664156783843838814410	386	UVM_INFO @ 407943767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	23826956600489099984845517554079211220978662751108084809905586271877356111145	386	UVM_INFO @ 408085352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	97356061092264813354556728505100263155944776139456974456915209057959409269727	386	UVM_INFO @ 302730162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	41428888529413429845340789586425985186181374261106273650110851548520876169680	386	UVM_INFO @ 499043283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	39307458322469175603283146651111999559661033820813421854510320460884449243244	386	UVM_INFO @ 509724597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	88477570183151699076516417408680812766727985939152576098515949923226502472445	386	UVM_INFO @ 495513331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	91811070590738573950570868666067482489274507355970149950748366172198495554597	386	UVM_INFO @ 406719175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	86424367424577107795870327998957989890374398254974260916059085572945091061605	413	UVM_INFO @ 1161328276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	109940007312999753903988753366175218749639173156813855892967201056415410549919	400	UVM_INFO @ 1282686603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	66534025472232052387196554703875572815877931679290502904301855925384888401625	386	UVM_INFO @ 342946232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	4420360768146233195508643876965289366911581011454660666131220062570236504689	386	UVM_INFO @ 415751990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	66197630327310396675783682197283424315818570287806608538567122100897422186477	386	UVM_INFO @ 366043398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	28852172253655475266256904006384198404179248833245576894782811616892423730993	386	UVM_INFO @ 484099957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	92334869902269405481086870690748923884161891209953048351928370534522344830042	386	UVM_INFO @ 353484274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	57203819520944309246610888274389341529328383709009242704214622047518543308697	386	UVM_INFO @ 470559962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	93372952721610941662333944304239420188947534109686839475263558977719268020220	386	UVM_INFO @ 393669134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	93291790033140192725835124550631018092271449150514350332103476436364939485035	386	UVM_INFO @ 281766828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	84329617885425264093151769882769575337860670524499224342517057390227132350534	421	UVM_INFO @ 2630658710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	96835967743248817423626491475343655721108116023545920584254904826461025553027	387	UVM_INFO @ 582883089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	26047920281990320628685742255589449819305086785207515550443954421733314620079	386	UVM_INFO @ 339796560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	87445377264164920414103276912021749738566263677982331013738904423339998986340	386	UVM_INFO @ 518978883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	71970951120245044402956052946941446987060517593294158091942105821163912275615	386	UVM_INFO @ 364957565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	104406331117926052200288915591878223985460245764137293123504863415234022304140	386	UVM_INFO @ 362880281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	84171656697861100091978044802933532832129525553076921624841621718610790508337	386	UVM_INFO @ 471579674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	103609621626362097978639904973577890223217708823213691181853696077019094820942	386	UVM_INFO @ 389266308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	17887606463854474360391974498004876902071826137619821687956617823776862547201	386	UVM_INFO @ 343139336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	20934996146252094509131229645137112203094799475603555944888722347063278653486	386	UVM_INFO @ 399349195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	83068002120728340987695947063798302249754733371224624960540818432845673608772	410	UVM_INFO @ 1666611391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---