| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 5 | 5 | 100.00 | |||
| aon_timer_smoke | 2.050s | 678.044us | 5 | 5 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| aon_timer_csr_hw_reset | 2.450s | 933.850us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| aon_timer_csr_rw | 1.650s | 431.614us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| aon_timer_csr_bit_bash | 8.930s | 13230.071us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| aon_timer_csr_aliasing | 1.890s | 465.026us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| aon_timer_csr_mem_rw_with_rand_reset | 1.350s | 518.222us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| aon_timer_csr_rw | 1.650s | 431.614us | 5 | 5 | 100.00 | |
| aon_timer_csr_aliasing | 1.890s | 465.026us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| aon_timer_mem_walk | 1.310s | 314.961us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| aon_timer_mem_partial_access | 1.080s | 345.336us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| prescaler | 15 | 15 | 100.00 | |||
| aon_timer_prescaler | 54.690s | 33959.511us | 15 | 15 | 100.00 | |
| jump | 5 | 5 | 100.00 | |||
| aon_timer_jump | 1.770s | 603.680us | 5 | 5 | 100.00 | |
| stress_all | 15 | 15 | 100.00 | |||
| aon_timer_stress_all | 214.420s | 158723.200us | 15 | 15 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| aon_timer_alert_test | 1.780s | 493.875us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| aon_timer_intr_test | 1.390s | 344.755us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| aon_timer_tl_errors | 3.760s | 571.370us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| aon_timer_tl_errors | 3.760s | 571.370us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| aon_timer_csr_hw_reset | 2.450s | 933.850us | 1 | 1 | 100.00 | |
| aon_timer_csr_rw | 1.650s | 431.614us | 5 | 5 | 100.00 | |
| aon_timer_csr_aliasing | 1.890s | 465.026us | 1 | 1 | 100.00 | |
| aon_timer_same_csr_outstanding | 2.570s | 1111.890us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| aon_timer_csr_hw_reset | 2.450s | 933.850us | 1 | 1 | 100.00 | |
| aon_timer_csr_rw | 1.650s | 431.614us | 5 | 5 | 100.00 | |
| aon_timer_csr_aliasing | 1.890s | 465.026us | 1 | 1 | 100.00 | |
| aon_timer_same_csr_outstanding | 2.570s | 1111.890us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| aon_timer_sec_cm | 8.110s | 8301.151us | 5 | 5 | 100.00 | |
| aon_timer_tl_intg_err | 17.310s | 8430.830us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| aon_timer_tl_intg_err | 17.310s | 8430.830us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_threshold | 5 | 5 | 100.00 | |||
| aon_timer_smoke_max_thold | 2.150s | 699.075us | 5 | 5 | 100.00 | |
| min_threshold | 5 | 5 | 100.00 | |||
| aon_timer_smoke_min_thold | 1.760s | 606.698us | 5 | 5 | 100.00 | |
| wkup_count_hi_cdc | 5 | 5 | 100.00 | |||
| aon_timer_wkup_count_cdc_hi | 11.540s | 3698.071us | 5 | 5 | 100.00 | |
| custom_intr | 10 | 10 | 100.00 | |||
| aon_timer_custom_intr | 1.460s | 671.682us | 10 | 10 | 100.00 | |
| alternating_on_off | 5 | 5 | 100.00 | |||
| aon_timer_alternating_enable_on_off | 20.520s | 4074.280us | 5 | 5 | 100.00 | |
| stress_all_with_rand_reset | 15 | 15 | 100.00 | |||
| aon_timer_stress_all_with_rand_reset | 43.010s | 72382.246us | 15 | 15 | 100.00 | |