Simulation Results: clkmgr

 
13/06/2026 02:15:06 DVSim: v1.49.0 sha: 9424e63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.88 %
  • code
  • 98.56 %
  • assert
  • 95.76 %
  • func
  • 87.31 %
  • line
  • 99.07 %
  • branch
  • 98.74 %
  • cond
  • 95.81 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.69%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
clkmgr_smoke 1.540s 126.106us 10 10 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.000s 27.664us 1 1 100.00
csr_rw 5 5 100.00
clkmgr_csr_rw 1.290s 69.533us 5 5 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 5.700s 290.933us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.380s 21.034us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.830s 83.710us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
clkmgr_csr_rw 1.290s 69.533us 5 5 100.00
clkmgr_csr_aliasing 1.380s 21.034us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 10 10 100.00
clkmgr_peri 1.310s 93.052us 10 10 100.00
trans_enables 10 10 100.00
clkmgr_trans 1.870s 227.158us 10 10 100.00
extclk 10 10 100.00
clkmgr_extclk 1.510s 159.940us 10 10 100.00
clk_status 10 10 100.00
clkmgr_clk_status 1.480s 189.895us 10 10 100.00
jitter 10 10 100.00
clkmgr_smoke 1.540s 126.106us 10 10 100.00
frequency 10 10 100.00
clkmgr_frequency 15.170s 2124.848us 10 10 100.00
frequency_timeout 10 10 100.00
clkmgr_frequency_timeout 13.050s 2182.559us 10 10 100.00
frequency_overflow 10 10 100.00
clkmgr_frequency 15.170s 2124.848us 10 10 100.00
stress_all 10 10 100.00
clkmgr_stress_all 79.410s 16549.225us 10 10 100.00
alert_test 10 10 100.00
clkmgr_alert_test 1.650s 165.947us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
clkmgr_tl_errors 7.340s 1451.072us 25 25 100.00
tl_d_illegal_access 25 25 100.00
clkmgr_tl_errors 7.340s 1451.072us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
clkmgr_csr_hw_reset 1.000s 27.664us 1 1 100.00
clkmgr_csr_rw 1.290s 69.533us 5 5 100.00
clkmgr_csr_aliasing 1.380s 21.034us 1 1 100.00
clkmgr_same_csr_outstanding 1.750s 73.776us 5 5 100.00
tl_d_partial_access 12 12 100.00
clkmgr_csr_hw_reset 1.000s 27.664us 1 1 100.00
clkmgr_csr_rw 1.290s 69.533us 5 5 100.00
clkmgr_csr_aliasing 1.380s 21.034us 1 1 100.00
clkmgr_same_csr_outstanding 1.750s 73.776us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 16 30 53.33
clkmgr_sec_cm 42.280s 10133.937us 0 5 0.00
clkmgr_tl_intg_err 64.890s 10036.546us 16 25 64.00
shadow_reg_update_error 14 20 70.00
clkmgr_shadow_reg_errors 964.880s 200000.000us 14 20 70.00
shadow_reg_read_clear_staged_value 14 20 70.00
clkmgr_shadow_reg_errors 964.880s 200000.000us 14 20 70.00
shadow_reg_storage_error 14 20 70.00
clkmgr_shadow_reg_errors 964.880s 200000.000us 14 20 70.00
shadowed_reset_glitch 14 20 70.00
clkmgr_shadow_reg_errors 964.880s 200000.000us 14 20 70.00
shadow_reg_update_error_with_csr_rw 13 20 65.00
clkmgr_shadow_reg_errors_with_csr_rw 786.620s 200000.000us 13 20 65.00
sec_cm_bus_integrity 16 25 64.00
clkmgr_tl_intg_err 64.890s 10036.546us 16 25 64.00
sec_cm_meas_clk_bkgn_chk 10 10 100.00
clkmgr_frequency 15.170s 2124.848us 10 10 100.00
sec_cm_timeout_clk_bkgn_chk 10 10 100.00
clkmgr_frequency_timeout 13.050s 2182.559us 10 10 100.00
sec_cm_meas_config_shadow 14 20 70.00
clkmgr_shadow_reg_errors 964.880s 200000.000us 14 20 70.00
sec_cm_idle_intersig_mubi 10 10 100.00
clkmgr_idle_intersig_mubi 1.400s 76.816us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
clkmgr_lc_ctrl_intersig_mubi 1.410s 134.004us 10 10 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 10 10 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.320s 70.311us 10 10 100.00
sec_cm_clk_handshake_intersig_mubi 9 10 90.00
clkmgr_clk_handshake_intersig_mubi 2.300s 278.325us 9 10 90.00
sec_cm_div_intersig_mubi 10 10 100.00
clkmgr_div_intersig_mubi 1.500s 125.479us 10 10 100.00
sec_cm_jitter_config_mubi 5 5 100.00
clkmgr_csr_rw 1.290s 69.533us 5 5 100.00
sec_cm_idle_ctr_redun 0 5 0.00
clkmgr_sec_cm 42.280s 10133.937us 0 5 0.00
sec_cm_meas_config_regwen 5 5 100.00
clkmgr_csr_rw 1.290s 69.533us 5 5 100.00
sec_cm_clk_ctrl_config_regwen 5 5 100.00
clkmgr_csr_rw 1.290s 69.533us 5 5 100.00
prim_count_check 0 5 0.00
clkmgr_sec_cm 42.280s 10133.937us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 10 10 100.00
clkmgr_regwen 6.290s 1265.082us 10 10 100.00
stress_all_with_rand_reset 10 10 100.00
clkmgr_stress_all_with_rand_reset 122.260s 20483.657us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 11 test runs
clkmgr_tl_intg_err 3778097395957421582098553772356330694724689023507376792223397124192677774434 136
UVM_INFO @ 10223405344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 107877196305301911238708602014242025978881125000959692792012129844247499113337 115
UVM_INFO @ 10076785697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 57807264991045066190237590784263502338737146044111276602157601210383057822850 164
UVM_INFO @ 10133937106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 61708634625631950932970036918736871101192991620249990536605728805382809445154 108
UVM_INFO @ 10100304158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 30025189330422692134713982762571994022030358384349892772146831140331656361290 103
UVM_INFO @ 10065346666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 91195085832402418198460486809522882994601761202282478687953261755231304424400 204
UVM_INFO @ 10218430894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 12549611394986531940726466292661258322538651582578569991980316009432953462267 258
UVM_INFO @ 10144998298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 61826218945655763364023870871001777246760416339685047121588341686955957819558 137
UVM_INFO @ 10036546302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 100022973996081341424426690351259921977056616896906706650858124879622196737570 82
UVM_INFO @ 10009866472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 101293981349761288425075222832975831316102365060367387701803191903516172171429 175
UVM_INFO @ 10123012674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 14896825925597532922288277908124201258872821383237279205383814697896721515263 120
UVM_INFO @ 10083907999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 9 test runs
clkmgr_shadow_reg_errors 35102040886356736418068598578585410966409612328967118743100199630960720575471 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 6061109405437187252381479104298429886930803593364032844860005404144310340541 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 100725091577725073781195012248939884586562942344240805737117870520522345488645 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 90263124773856267899497592246914419226333820006856831579816739995312857616694 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 34558473605475789493013052121511424505080981311533968170177970853875617112325 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 60216931521691248931874691988694381348112127687023281806534587158412495170558 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 43062713778029445109556080084578181296254553103878208012365487177727769751175 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 28656664386324518204310909255482623177001614293033000672478605184541943633535 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 59789016213985759060567909083599939299775183577675594936421190259387523568074 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 3 test runs
clkmgr_sec_cm 56630418881557455550789018030487967008178487393871604156309908439404883051947 97
UVM_INFO @ 29988859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 7054936534873339671735065709813742772025077288712757477673499767799277137030 84
UVM_INFO @ 11861850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 73920769276116308534560941229122674222564702831213437896991511900080801910960 77
UVM_INFO @ 1721559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.clk_hints_status (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 93462422446627949370676042528297465543364872022632626965165954756618805204800 76
UVM_INFO @ 2100578628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [*] vs * [*]) extclk_status mismatch 1 test run
clkmgr_clk_handshake_intersig_mubi 27681250007167605391035681124285495859507132426076297226549224105771911658388 74
UVM_INFO @ 6173085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.extclk_ctrl_regwen (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 88661472796540005118157251186134042821985761775289833289838693764484543269702 75
UVM_INFO @ 2195510316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.clk_enables (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 2077682102788589481195324317762692418649129020528550685655839860958099361705 75
UVM_INFO @ 2056368625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 47410862415011498480097145308080318314956776960799712934407105572283921774281 75
UVM_INFO @ 39497409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---