Simulation Results

Simulation Results: csrng

13/06/2026 02:15:06 DVSim: v1.49.0 sha: 9424e63 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.62 %

code
96.20 %

assert
97.16 %

func
90.50 %

block
98.53 %

line
99.54 %

branch
96.38 %

toggle
93.64 %

FSM
95.24 %

Validation stages

V1		100.00%
V2		98.16%
V2S		98.83%
V3		0.00%

38/38 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				25	25	100.00
	csrng_smoke	26.000s	26.120us	25	25	100.00
csr_hw_reset				1	1	100.00
	csrng_csr_hw_reset	36.000s	29.016us	1	1	100.00
csr_rw				5	5	100.00
	csrng_csr_rw	35.000s	15.354us	5	5	100.00
csr_bit_bash				1	1	100.00
	csrng_csr_bit_bash	43.000s	317.117us	1	1	100.00
csr_aliasing				1	1	100.00
	csrng_csr_aliasing	38.000s	141.022us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	csrng_csr_mem_rw_with_rand_reset	36.000s	31.605us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	csrng_csr_rw	35.000s	15.354us	5	5	100.00
	csrng_csr_aliasing	38.000s	141.022us	1	1	100.00

1283/1307 passed

98.16 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				200	200	100.00
	csrng_intr	41.000s	347.485us	200	200	100.00
alerts				500	500	100.00
	csrng_alert	53.000s	4415.199us	500	500	100.00
err				500	500	100.00
	csrng_err	35.000s	21.298us	500	500	100.00
cmds				2	25	8.00
	csrng_cmds	173.000s	13848.696us	2	25	8.00
life cycle				2	25	8.00
	csrng_cmds	173.000s	13848.696us	2	25	8.00
stress_all				24	25	96.00
	csrng_stress_all	1310.000s	58759.154us	24	25	96.00
intr_test				10	10	100.00
	csrng_intr_test	33.000s	53.261us	10	10	100.00
alert_test				10	10	100.00
	csrng_alert_test	36.000s	13.366us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	csrng_tl_errors	26.000s	241.477us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	csrng_tl_errors	26.000s	241.477us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	csrng_csr_hw_reset	36.000s	29.016us	1	1	100.00
	csrng_csr_rw	35.000s	15.354us	5	5	100.00
	csrng_csr_aliasing	38.000s	141.022us	1	1	100.00
	csrng_same_csr_outstanding	32.000s	56.359us	5	5	100.00
tl_d_partial_access				12	12	100.00
	csrng_csr_hw_reset	36.000s	29.016us	1	1	100.00
	csrng_csr_rw	35.000s	15.354us	5	5	100.00
	csrng_csr_aliasing	38.000s	141.022us	1	1	100.00
	csrng_same_csr_outstanding	32.000s	56.359us	5	5	100.00

V2S

1270/1285 passed

98.83 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	csrng_sec_cm	28.000s	65.646us	5	5	100.00
	csrng_tl_intg_err	38.000s	3460.769us	25	25	100.00
sec_cm_config_regwen				16	30	53.33
	csrng_regwen	32.000s	15.238us	11	25	44.00
	csrng_csr_rw	35.000s	15.354us	5	5	100.00
sec_cm_config_mubi				500	500	100.00
	csrng_alert	53.000s	4415.199us	500	500	100.00
sec_cm_intersig_mubi				24	25	96.00
	csrng_stress_all	1310.000s	58759.154us	24	25	96.00
sec_cm_main_sm_fsm_sparse				705	705	100.00
	csrng_intr	41.000s	347.485us	200	200	100.00
	csrng_err	35.000s	21.298us	500	500	100.00
	csrng_sec_cm	28.000s	65.646us	5	5	100.00
sec_cm_cmd_stage_fsm_sparse				705	705	100.00
	csrng_intr	41.000s	347.485us	200	200	100.00
	csrng_err	35.000s	21.298us	500	500	100.00
	csrng_sec_cm	28.000s	65.646us	5	5	100.00
sec_cm_ctr_drbg_fsm_sparse				705	705	100.00
	csrng_intr	41.000s	347.485us	200	200	100.00
	csrng_err	35.000s	21.298us	500	500	100.00
	csrng_sec_cm	28.000s	65.646us	5	5	100.00
sec_cm_ctr_drbg_ctr_redun				705	705	100.00
	csrng_intr	41.000s	347.485us	200	200	100.00
	csrng_err	35.000s	21.298us	500	500	100.00
	csrng_sec_cm	28.000s	65.646us	5	5	100.00
sec_cm_gen_cmd_ctr_redun				705	705	100.00
	csrng_intr	41.000s	347.485us	200	200	100.00
	csrng_err	35.000s	21.298us	500	500	100.00
	csrng_sec_cm	28.000s	65.646us	5	5	100.00
sec_cm_ctrl_mubi				500	500	100.00
	csrng_alert	53.000s	4415.199us	500	500	100.00
sec_cm_main_sm_ctr_local_esc				700	700	100.00
	csrng_intr	41.000s	347.485us	200	200	100.00
	csrng_err	35.000s	21.298us	500	500	100.00
sec_cm_constants_lc_gated				24	25	96.00
	csrng_stress_all	1310.000s	58759.154us	24	25	96.00
sec_cm_sw_genbits_bus_consistency				500	500	100.00
	csrng_alert	53.000s	4415.199us	500	500	100.00
sec_cm_tile_link_bus_integrity				25	25	100.00
	csrng_tl_intg_err	38.000s	3460.769us	25	25	100.00
sec_cm_aes_cipher_fsm_sparse				705	705	100.00
	csrng_intr	41.000s	347.485us	200	200	100.00
	csrng_err	35.000s	21.298us	500	500	100.00
	csrng_sec_cm	28.000s	65.646us	5	5	100.00
sec_cm_aes_cipher_fsm_redun				700	700	100.00
	csrng_intr	41.000s	347.485us	200	200	100.00
	csrng_err	35.000s	21.298us	500	500	100.00
sec_cm_aes_cipher_ctrl_sparse				700	700	100.00
	csrng_intr	41.000s	347.485us	200	200	100.00
	csrng_err	35.000s	21.298us	500	500	100.00
sec_cm_aes_cipher_fsm_local_esc				700	700	100.00
	csrng_intr	41.000s	347.485us	200	200	100.00
	csrng_err	35.000s	21.298us	500	500	100.00
sec_cm_aes_cipher_ctr_redun				705	705	100.00
	csrng_intr	41.000s	347.485us	200	200	100.00
	csrng_err	35.000s	21.298us	500	500	100.00
	csrng_sec_cm	28.000s	65.646us	5	5	100.00
sec_cm_aes_cipher_data_reg_local_esc				700	700	100.00
	csrng_intr	41.000s	347.485us	200	200	100.00
	csrng_err	35.000s	21.298us	500	500	100.00

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	csrng_stress_all_with_rand_reset	3601.000s	0.000us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [] vs [*])				21 test runs
	csrng_cmds	57456021451659395641530857865136792076879324606109416115689236685678188587470	100	UVM_INFO @ 273758016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	76612143812702859066809560621804728729896613452877606206331527246747340253109	100	UVM_INFO @ 373781578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	58684051878989695017725996531920277266568311328120047056989427671393664495668	100	UVM_INFO @ 26777361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	110905312553058248423837850850410938532368819050261477984201328111680926061376	100	UVM_INFO @ 103312193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	39319949648263129106882132265048621299818624047161192247710988331479063074291	130	UVM_INFO @ 1171664566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	61933501851035940113781438418823081079616087039126427976682186526487919102461	100	UVM_INFO @ 96057370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	1283460226616903700918559626988630204996944962214400457282198919850352262398	100	UVM_INFO @ 198385153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	12259350102120728902599122290872344357274665915449384328582407421584937689080	100	UVM_INFO @ 49106321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	60309055841925475336179487546492816351301094544286987039283714043229385046776	100	UVM_INFO @ 183925517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	68950500071450572687044313763453802607198778745028599310705796431419613009535	110	UVM_INFO @ 21562959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	56602994673726136800079122754003071832195343633426583305271430600830540894815	109	UVM_INFO @ 39723002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	71834612668489073764789848238700592649184608040286314301460042300117390611397	100	UVM_INFO @ 205936878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	15461192560691210091824927478754500186732542489329212897402594174374767797562	100	UVM_INFO @ 152134007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	93875738754219759594980013962408998613850239664456079579287145211377040829182	100	UVM_INFO @ 83617689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	112169676042889374432058599570087169259260336240220428005219877425962929021766	100	UVM_INFO @ 47624237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	77039953555602259391306071845882167863321923368566060450357112172767172330686	100	UVM_INFO @ 18326941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	20441904478398835735771816307054205798260433573623666236433692630194277555641	100	UVM_INFO @ 79927895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	65683439344519064037749636858315938220209526464515585896971101178025925675289	100	UVM_INFO @ 88805399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	37246300769911357994885497906418473979576817696985870283841747125548645460255	100	UVM_INFO @ 33881396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	100923112423843017772678627491689829609185677384826995191876199019064887987887	100	UVM_INFO @ 946136127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	40874454534438281053231952807373490176971839613933588099859116437689192593861	100	UVM_INFO @ 423067839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE				11 test runs
	csrng_regwen	6296243874674886613986930251734359200668982926346153645895585650191658354593	99	UVM_INFO @ 12638921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	31899976513931719621152705397727689089631722065701372135671888610235404147937	99	UVM_INFO @ 5907484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	65326937953768116155500350998439518140606385428889204577025204260420320929119	99	UVM_INFO @ 3868528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	57958284178120576204762624604728456553678818213850476073001938383200418183495	99	UVM_INFO @ 35819604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	65630814230401222343726422663505470621961034879264589264297017099424927538965	99	UVM_INFO @ 6757496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	89685648840508124832717707344832193294413192031997485042486016158084384939874	99	UVM_INFO @ 4876051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	98589957587778482978830226671328051227293778933785671827472384161887592382169	99	UVM_INFO @ 5847972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	80344327587652036858816439311027742642668787934928147773340991049150408969583	99	UVM_INFO @ 1509435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	23468457877186317067673558271131980147492183123519976772862576280177012221800	99	UVM_INFO @ 5163099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	48503642252469278643858300154251155397865095881734868885097422766674903369257	99	UVM_INFO @ 3970573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	88404778758483272969346096529309903542064142705448394478107558999111219268562	99	UVM_INFO @ 3031204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				7 test runs
	csrng_stress_all_with_rand_reset	79752820968710323971885552409219313430136835964191298779195478993521643915234	None
	csrng_stress_all_with_rand_reset	19570404742242181185414068391854903598983526478394091284227671756203510816023	None
	csrng_stress_all_with_rand_reset	86391810593048865897017760507748869447588093377326781849526875256891220400601	None
	csrng_stress_all_with_rand_reset	93084576923356916070037210988292000344426762114552248310024286548706885798742	None
	csrng_stress_all_with_rand_reset	52375315437283349592654375583897092345350114277540498561593634099209628865878	None
	csrng_stress_all_with_rand_reset	13987075734915187445224864525443886688016529249849880901346982237677994997136	None
	csrng_stress_all_with_rand_reset	78243121721443285109124311684097942994035723255864157099198797104254307570497	None
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [] vs [*]) Interrupt_pin: EntropyReq				3 test runs
	csrng_stress_all_with_rand_reset	67456576514878212294350585637588009169126799596276774844673618742858633910330	113	UVM_INFO @ 135016925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	48665011030006465347922355003371428838970043008522578938329373372948390795565	141	UVM_INFO @ 4304573867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	17387004259239446275486922998671581198660851425680977194931709195916370794225	113	UVM_INFO @ 2291699917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE				3 test runs
	csrng_regwen	31874622136139222157126735081694879376174928332564940408897206040749509611636	99	UVM_INFO @ 1587938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	103304559860477109658908611675798466235385842570518392511209274263407756792759	99	UVM_INFO @ 6724541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	28555584246092416624644277352494486246018237041457788035058859942050147549992	99	UVM_INFO @ 3392251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started				1 test run
	csrng_stress_all_with_rand_reset	57053408955016689155755078466444580033425287022704196701288474007961384563740	114	UVM_INFO @ 41028118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:640) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [] vs [*])				1 test run
	csrng_cmds	26781777401539599912914911637958590388256978990215445471913888025939156007176	109	UVM_INFO @ 59782510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert recov_alert triggered unexpectedly				1 test run
	csrng_cmds	52052621090005114480778325830089870502583354258751508389622864944740817344368	108	UVM_INFO @ 10289506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---