Simulation Results: edn/edn0

 
13/06/2026 02:15:06 DVSim: v1.49.0 sha: 9424e63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.79 %
  • code
  • 95.78 %
  • assert
  • 98.92 %
  • func
  • 92.66 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 93.91 %
  • toggle
  • 97.12 %
  • FSM
  • 92.47 %
Validation stages
V1
100.00%
V2
99.51%
V2S
100.00%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.220s 28.812us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.440s 20.739us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.260s 20.306us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.630s 322.808us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.220s 138.205us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.580s 26.395us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.260s 20.306us 5 5 100.00
edn_csr_aliasing 1.220s 138.205us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 5.590s 678.771us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 5.590s 678.771us 100 100 100.00
genbits 100 100 100.00
edn_genbits 5.590s 678.771us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.430s 24.439us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.750s 491.493us 200 200 100.00
errs 100 100 100.00
edn_err 1.890s 38.288us 100 100 100.00
disable 97 100 97.00
edn_disable 1.280s 26.106us 50 50 100.00
edn_disable_auto_req_mode 8.230s 500.000us 47 50 94.00
stress_all 30 30 100.00
edn_stress_all 8.940s 425.585us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.370s 19.305us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.270s 53.267us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 3.960s 755.261us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 3.960s 755.261us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.440s 20.739us 1 1 100.00
edn_csr_rw 1.260s 20.306us 5 5 100.00
edn_csr_aliasing 1.220s 138.205us 1 1 100.00
edn_same_csr_outstanding 1.660s 39.659us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.440s 20.739us 1 1 100.00
edn_csr_rw 1.260s 20.306us 5 5 100.00
edn_csr_aliasing 1.220s 138.205us 1 1 100.00
edn_same_csr_outstanding 1.660s 39.659us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 4.280s 1907.361us 5 5 100.00
edn_tl_intg_err 5.720s 1769.852us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.120s 54.824us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.750s 491.493us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.280s 1907.361us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.280s 1907.361us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 4.280s 1907.361us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 4.280s 1907.361us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.750s 491.493us 200 200 100.00
edn_sec_cm 4.280s 1907.361us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.750s 491.493us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 5.720s 1769.852us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 21 30 70.00
edn_stress_all_with_rand_reset 127.680s 11651.841us 21 30 70.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 7 test runs
edn_stress_all_with_rand_reset 28230418390415500114340850014951935685807582973064887659621646105145562469748 191
UVM_INFO @ 1924857066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 42082563322441368317597199496117335680388650569261887839807467854961641840376 240
UVM_INFO @ 2369422942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 108058838757954238423581807149768275822655031430527597837308132887235774819358 244
UVM_INFO @ 3487460218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 35221893982146117102388451109985844165904532445706007404949553711664794626794 328
UVM_INFO @ 1978025592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 100560749723850360239553128082809468918344279057472125431318025783636098018337 214
UVM_INFO @ 1913424306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 104413172697804561697996401046748855227421699845351818311875172990372892967135 359
UVM_INFO @ 4005924518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 48719141980929367547895370058163157379761302223852459075941497529417981577113 305
UVM_INFO @ 2761582309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 3 test runs
edn_disable_auto_req_mode 22265938587450556037487132736859737737955041351525936700721212783881844385993 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 71282132849970466165188749843156714284693808707379161297080558541299326292229 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 66728061790241751985460166618565866780942212327326787873740578747095259639960 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 2 test runs
edn_stress_all_with_rand_reset 49146246451840792722169486130448884136384429433881472929174778315627303377157 156
UVM_INFO @ 11994773454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 98979906308329869376115726831151286412983731932320354861114901705214167819104 289
UVM_INFO @ 11651841333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---