Simulation Results: edn/edn1

 
13/06/2026 02:15:06 DVSim: v1.49.0 sha: 9424e63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.66 %
  • code
  • 96.30 %
  • assert
  • 98.44 %
  • func
  • 92.23 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 94.54 %
  • toggle
  • 96.15 %
  • FSM
  • 97.73 %
Validation stages
V1
100.00%
V2
98.85%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 0.970s 24.064us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.850s 46.013us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.060s 69.868us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.700s 87.143us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.230s 58.165us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.350s 104.367us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.060s 69.868us 5 5 100.00
edn_csr_aliasing 1.230s 58.165us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 4.760s 675.683us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 4.760s 675.683us 100 100 100.00
genbits 100 100 100.00
edn_genbits 4.760s 675.683us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.070s 39.983us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.690s 340.659us 200 200 100.00
errs 100 100 100.00
edn_err 1.570s 106.419us 100 100 100.00
disable 93 100 93.00
edn_disable 1.040s 13.815us 50 50 100.00
edn_disable_auto_req_mode 1.820s 500.000us 43 50 86.00
stress_all 30 30 100.00
edn_stress_all 6.320s 1106.543us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.060s 69.397us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 0.980s 19.344us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 3.450s 209.215us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 3.450s 209.215us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 0.850s 46.013us 1 1 100.00
edn_csr_rw 1.060s 69.868us 5 5 100.00
edn_csr_aliasing 1.230s 58.165us 1 1 100.00
edn_same_csr_outstanding 1.230s 77.448us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 0.850s 46.013us 1 1 100.00
edn_csr_rw 1.060s 69.868us 5 5 100.00
edn_csr_aliasing 1.230s 58.165us 1 1 100.00
edn_same_csr_outstanding 1.230s 77.448us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 4.780s 470.801us 5 5 100.00
edn_tl_intg_err 2.710s 204.068us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.050s 18.008us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.690s 340.659us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.780s 470.801us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.780s 470.801us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 4.780s 470.801us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 4.780s 470.801us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.690s 340.659us 200 200 100.00
edn_sec_cm 4.780s 470.801us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.690s 340.659us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 2.710s 204.068us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 27 30 90.00
edn_stress_all_with_rand_reset 122.560s 34262.334us 27 30 90.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 5 test runs
edn_disable_auto_req_mode 49434023857590009735371576959990011509261155569012192008835446688682112611497 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 16459856049394252920749881305932923869634763027299534661012395857323246732879 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 107300087434070042282956706407961227800285627388333054138334984961619374569704 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 25217618856654155027115025701067856180437881520516647152319232292062829659485 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 88398614037070528524570939957102286469324366073557854513507989184015193034004 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
edn_stress_all_with_rand_reset 26589762408686980506034200551739576957882117883328965491080993489971621279319 172
UVM_INFO @ 1462181063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 10234622536334244392453567507276042252390462225378654855629705306636160714254 168
UVM_INFO @ 1645207524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 28404252488190827889341062416368146787629530440460267109394664415908011985273 265
UVM_INFO @ 2202353623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 2 test runs
edn_disable_auto_req_mode 102185364457275644699567194087705492700284657939820302691942877862680164583818 88
UVM_INFO @ 17421204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 54734876881400553844460646928412956096217769274306863071888632429358010083833 88
UVM_INFO @ 24110836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---