Simulation Results: flash_ctrl

 
13/06/2026 02:15:06 DVSim: v1.49.0 sha: 9424e63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.07 %
  • code
  • 95.81 %
  • assert
  • 97.02 %
  • func
  • 98.39 %
  • line
  • 96.11 %
  • branch
  • 97.45 %
  • cond
  • 94.98 %
  • toggle
  • 98.66 %
  • FSM
  • 91.84 %
Validation stages
V1
100.00%
V2
98.61%
V2S
98.95%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
flash_ctrl_smoke 182.320s 106.672us 50 50 100.00
smoke_hw 5 5 100.00
flash_ctrl_smoke_hw 24.770s 59.141us 5 5 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 17.920s 536.400us 1 1 100.00
csr_rw 5 5 100.00
flash_ctrl_csr_rw 16.880s 259.844us 5 5 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 49.830s 947.755us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 29.120s 3544.398us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 14.140s 52.839us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
flash_ctrl_csr_rw 16.880s 259.844us 5 5 100.00
flash_ctrl_csr_aliasing 29.120s 3544.398us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 12.910s 54.523us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 13.290s 31.727us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 5 5 100.00
flash_ctrl_sw_op 21.020s 107.471us 5 5 100.00
host_read_direct 5 5 100.00
flash_ctrl_host_dir_rd 73.570s 78.779us 5 5 100.00
rma_hw_if 43 43 100.00
flash_ctrl_hw_rma 1432.560s 171863.452us 3 3 100.00
flash_ctrl_hw_rma_reset 768.690s 140176.363us 20 20 100.00
flash_ctrl_lcmgr_intg 13.970s 43.146us 20 20 100.00
host_controller_arb 5 5 100.00
flash_ctrl_host_ctrl_arb 1475.410s 523582.747us 5 5 100.00
erase_suspend 5 5 100.00
flash_ctrl_erase_suspend 304.580s 2715.021us 5 5 100.00
program_reset 29 30 96.67
flash_ctrl_prog_reset 2858.460s 500000.000us 29 30 96.67
full_memory_access 5 5 100.00
flash_ctrl_full_mem_access 2901.070s 169052.950us 5 5 100.00
rd_buff_eviction 5 5 100.00
flash_ctrl_rd_buff_evict 82.930s 1880.805us 5 5 100.00
rd_buff_eviction_w_ecc 102 105 97.14
flash_ctrl_rw_evict 35.450s 63.191us 38 40 95.00
flash_ctrl_rw_evict_all_en 35.130s 34.970us 39 40 97.50
flash_ctrl_re_evict 36.430s 304.092us 25 25 100.00
host_arb 20 20 100.00
flash_ctrl_phy_arb 212.760s 2469.264us 20 20 100.00
host_interleave 20 20 100.00
flash_ctrl_phy_arb 212.760s 2469.264us 20 20 100.00
memory_protection 20 20 100.00
flash_ctrl_mp_regions 616.460s 50502.951us 20 20 100.00
fetch_code 10 10 100.00
flash_ctrl_fetch_code 25.050s 350.635us 10 10 100.00
all_partitions 20 20 100.00
flash_ctrl_rand_ops 723.190s 6019.504us 20 20 100.00
error_mp 10 10 100.00
flash_ctrl_error_mp 566.330s 5828.575us 10 10 100.00
error_prog_win 10 10 100.00
flash_ctrl_error_prog_win 609.660s 1178.166us 10 10 100.00
error_prog_type 5 5 100.00
flash_ctrl_error_prog_type 1422.150s 4840.684us 5 5 100.00
error_read_seed 20 20 100.00
flash_ctrl_hw_read_seed_err 14.780s 75.014us 20 20 100.00
read_write_overflow 5 5 100.00
flash_ctrl_oversize_error 150.970s 6032.587us 5 5 100.00
flash_ctrl_disable 50 50 100.00
flash_ctrl_disable 24.410s 33.725us 50 50 100.00
flash_ctrl_connect 80 80 100.00
flash_ctrl_connect 18.140s 26.841us 80 80 100.00
stress_all 5 5 100.00
flash_ctrl_stress_all 966.850s 824.342us 5 5 100.00
secret_partition 130 130 100.00
flash_ctrl_hw_sec_otp 177.260s 6341.858us 50 50 100.00
flash_ctrl_otp_reset 120.880s 43.675us 80 80 100.00
isolation_partition 3 3 100.00
flash_ctrl_hw_rma 1432.560s 171863.452us 3 3 100.00
interrupts 96 100 96.00
flash_ctrl_intr_rd 184.370s 3831.076us 37 40 92.50
flash_ctrl_intr_wr 70.700s 4770.491us 10 10 100.00
flash_ctrl_intr_rd_slow_flash 385.620s 211799.868us 40 40 100.00
flash_ctrl_intr_wr_slow_flash 3604.015s 0.000us 9 10 90.00
invalid_op 20 20 100.00
flash_ctrl_invalid_op 73.110s 11356.280us 20 20 100.00
mid_op_rst 5 5 100.00
flash_ctrl_mid_op_rst 56.560s 1047.829us 5 5 100.00
double_bit_err 34 35 97.14
flash_ctrl_read_word_sweep_derr 22.400s 40.542us 5 5 100.00
flash_ctrl_ro_derr 115.340s 768.965us 10 10 100.00
flash_ctrl_rw_derr 163.760s 8003.337us 10 10 100.00
flash_ctrl_derr_detect 154.930s 2503.446us 4 5 80.00
flash_ctrl_integrity 474.060s 71930.647us 5 5 100.00
single_bit_err 25 25 100.00
flash_ctrl_read_word_sweep_serr 18.270s 28.145us 5 5 100.00
flash_ctrl_ro_serr 113.570s 773.114us 10 10 100.00
flash_ctrl_rw_serr 155.910s 5084.020us 10 10 100.00
singlebit_err_counter 5 5 100.00
flash_ctrl_serr_counter 57.530s 1171.746us 5 5 100.00
singlebit_err_address 5 5 100.00
flash_ctrl_serr_address 60.650s 949.727us 5 5 100.00
scramble 59 62 95.16
flash_ctrl_wo 168.540s 36837.541us 20 20 100.00
flash_ctrl_write_word_sweep 11.460s 540.939us 1 1 100.00
flash_ctrl_read_word_sweep 14.210s 259.798us 1 1 100.00
flash_ctrl_ro 113.860s 4803.886us 20 20 100.00
flash_ctrl_rw 428.950s 9124.253us 17 20 85.00
filesystem_support 4 5 80.00
flash_ctrl_fs_sup 37.670s 785.811us 4 5 80.00
rma_write_process_error 23 23 100.00
flash_ctrl_rma_err 695.630s 92049.818us 3 3 100.00
flash_ctrl_hw_prog_rma_wipe_err 237.880s 10019.832us 20 20 100.00
alert_test 10 10 100.00
flash_ctrl_alert_test 14.080s 124.832us 10 10 100.00
intr_test 10 10 100.00
flash_ctrl_intr_test 15.070s 31.059us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
flash_ctrl_tl_errors 20.720s 65.756us 25 25 100.00
tl_d_illegal_access 25 25 100.00
flash_ctrl_tl_errors 20.720s 65.756us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
flash_ctrl_csr_hw_reset 17.920s 536.400us 1 1 100.00
flash_ctrl_csr_rw 16.880s 259.844us 5 5 100.00
flash_ctrl_csr_aliasing 29.120s 3544.398us 1 1 100.00
flash_ctrl_same_csr_outstanding 26.170s 2378.948us 5 5 100.00
tl_d_partial_access 12 12 100.00
flash_ctrl_csr_hw_reset 17.920s 536.400us 1 1 100.00
flash_ctrl_csr_rw 16.880s 259.844us 5 5 100.00
flash_ctrl_csr_aliasing 29.120s 3544.398us 1 1 100.00
flash_ctrl_same_csr_outstanding 26.170s 2378.948us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
flash_ctrl_shadow_reg_errors 81.170s 45.476us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
flash_ctrl_shadow_reg_errors 81.170s 45.476us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
flash_ctrl_shadow_reg_errors 81.170s 45.476us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
flash_ctrl_shadow_reg_errors 81.170s 45.476us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 96.720s 1261.655us 20 20 100.00
tl_intg_err 30 30 100.00
flash_ctrl_sec_cm 2458.600s 2991.763us 5 5 100.00
flash_ctrl_tl_intg_err 645.100s 1825.197us 25 25 100.00
sec_cm_reg_bus_integrity 25 25 100.00
flash_ctrl_tl_intg_err 645.100s 1825.197us 25 25 100.00
sec_cm_host_bus_integrity 25 25 100.00
flash_ctrl_tl_intg_err 645.100s 1825.197us 25 25 100.00
sec_cm_mem_bus_integrity 6 6 100.00
flash_ctrl_rd_intg 23.160s 127.166us 3 3 100.00
flash_ctrl_wr_intg 12.500s 97.118us 3 3 100.00
sec_cm_scramble_key_sideload 50 50 100.00
flash_ctrl_smoke 182.320s 106.672us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 260 260 100.00
flash_ctrl_otp_reset 120.880s 43.675us 80 80 100.00
flash_ctrl_disable 24.410s 33.725us 50 50 100.00
flash_ctrl_sec_info_access 80.490s 37839.412us 50 50 100.00
flash_ctrl_connect 18.140s 26.841us 80 80 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
flash_ctrl_config_regwen 13.900s 23.326us 5 5 100.00
sec_cm_data_regions_config_regwen 5 5 100.00
flash_ctrl_csr_rw 16.880s 259.844us 5 5 100.00
sec_cm_data_regions_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 81.170s 45.476us 20 20 100.00
sec_cm_info_regions_config_regwen 5 5 100.00
flash_ctrl_csr_rw 16.880s 259.844us 5 5 100.00
sec_cm_info_regions_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 81.170s 45.476us 20 20 100.00
sec_cm_bank_config_regwen 5 5 100.00
flash_ctrl_csr_rw 16.880s 259.844us 5 5 100.00
sec_cm_bank_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 81.170s 45.476us 20 20 100.00
sec_cm_mem_ctrl_global_esc 50 50 100.00
flash_ctrl_disable 24.410s 33.725us 50 50 100.00
sec_cm_mem_ctrl_local_esc 6 6 100.00
flash_ctrl_rd_intg 23.160s 127.166us 3 3 100.00
flash_ctrl_access_after_disable 11.320s 77.882us 3 3 100.00
sec_cm_mem_addr_infection 3 3 100.00
flash_ctrl_host_addr_infection 19.080s 28.426us 3 3 100.00
sec_cm_mem_disable_config_mubi 50 50 100.00
flash_ctrl_disable 24.410s 33.725us 50 50 100.00
sec_cm_exec_config_redun 10 10 100.00
flash_ctrl_fetch_code 25.050s 350.635us 10 10 100.00
sec_cm_mem_scramble 17 20 85.00
flash_ctrl_rw 428.950s 9124.253us 17 20 85.00
sec_cm_mem_integrity 25 25 100.00
flash_ctrl_rw_serr 155.910s 5084.020us 10 10 100.00
flash_ctrl_rw_derr 163.760s 8003.337us 10 10 100.00
flash_ctrl_integrity 474.060s 71930.647us 5 5 100.00
sec_cm_rma_entry_mem_sec_wipe 3 3 100.00
flash_ctrl_hw_rma 1432.560s 171863.452us 3 3 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2458.600s 2991.763us 5 5 100.00
sec_cm_phy_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2458.600s 2991.763us 5 5 100.00
sec_cm_phy_prog_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2458.600s 2991.763us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
flash_ctrl_sec_cm 2458.600s 2991.763us 5 5 100.00
sec_cm_phy_arbiter_ctrl_redun 5 5 100.00
flash_ctrl_phy_arb_redun 23.040s 925.548us 5 5 100.00
sec_cm_phy_host_grant_ctrl_consistency 3 5 60.00
flash_ctrl_phy_host_grant_err 13.870s 41.689us 3 5 60.00
sec_cm_phy_ack_ctrl_consistency 5 5 100.00
flash_ctrl_phy_ack_consistency 14.190s 78.287us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
flash_ctrl_sec_cm 2458.600s 2991.763us 5 5 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2458.600s 2991.763us 5 5 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2458.600s 2991.763us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 31.070s 250.058us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 3 3 100.00
flash_ctrl_basic_rw 534.180s 1388.264us 3 3 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly 3 test runs
flash_ctrl_rw 58306294587212333443280778793622138203214757151681725886266790673678145117100 108
UVM_INFO @ 7034010.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_rw 62189558184428937393212996394890393832105455750547478265262848980445579653204 108
UVM_INFO @ 15660823.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_rw 30432234930797074780337513650336693351443562884240038142972125135179490998983 108
UVM_INFO @ 7222509.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' 2 test runs
flash_ctrl_phy_host_grant_err 19590310202912321060161783526663722466090791007259659668320220857684101606086 125
UVM_ERROR @ 11449.9 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 11449.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_phy_host_grant_err 65631495245633859114620442791698665501560840779726123838365947384290614237791 125
UVM_ERROR @ 11648.8 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 11648.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly 2 test runs
flash_ctrl_fs_sup 98801743894373751368742650573828620632893180905680813914241255010400710618453 108
UVM_INFO @ 712679.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_derr_detect 36354732905455874700364184958829740026164009005938736229513799807041616764665 129
UVM_INFO @ 475009.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * 2 test runs
flash_ctrl_rw_evict 77715187129623652785358367813318485457201684511666357401171859482293200040634 108
UVM_INFO @ 40468.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_rw_evict_all_en 21025762979757586456123921909845175343572020617859011427311940662889218405241 108
UVM_INFO @ 14087.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
flash_ctrl_intr_wr_slow_flash 1451395355387689538374837639874342373158575382953704901366190113016475400725 None
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * 1 test run
flash_ctrl_rw_evict 81911159464119963222735649744193619924021995605235409811502405526614296675622 108
UVM_INFO @ 13942.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp d33ec27c_506fa624:ffffffff_ffffffff mismatch!! 1 test run
flash_ctrl_intr_rd 11235505982163556124845828763933304502071641769404581116792425575104646385408 108
UVM_INFO @ 4136649.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ns hit, indicating a probable testbench issue 1 test run
flash_ctrl_prog_reset 97747548680011601626914804058115952519614267478232652773366747988008185312154 108
UVM_INFO @ 500000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp *c6bf00_83250f8b:ffffffff_ffffffff mismatch!! 1 test run
flash_ctrl_intr_rd 47115474742133901416171863407432287109750308021952114906332191574181989409236 108
UVM_INFO @ 1558588.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp *dde23fc_d4348dba:ffffffff_ffffffff mismatch!! 1 test run
flash_ctrl_intr_rd 25808878181289799738640156068929324879748086533037079398952533685307824270924 108
UVM_INFO @ 4508680.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---