Simulation Results: gpio

 
13/06/2026 02:15:06 DVSim: v1.49.0 sha: 9424e63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.79 %
  • code
  • 98.27 %
  • assert
  • 98.10 %
  • func
  • 100.00 %
  • line
  • 99.76 %
  • branch
  • 99.80 %
  • cond
  • 99.57 %
  • toggle
  • 93.94 %
Validation stages
V1
100.00%
V2
94.90%
V2S
100.00%
V3
35.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 40 40 100.00
gpio_smoke 1.890s 98.278us 10 10 100.00
gpio_smoke_no_pullup_pulldown 1.480s 172.313us 10 10 100.00
gpio_smoke_en_cdc_prim 1.690s 296.959us 10 10 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.940s 108.996us 10 10 100.00
csr_hw_reset 1 1 100.00
gpio_csr_hw_reset 0.990s 67.024us 1 1 100.00
csr_rw 5 5 100.00
gpio_csr_rw 1.020s 47.942us 5 5 100.00
csr_bit_bash 1 1 100.00
gpio_csr_bit_bash 3.650s 232.732us 1 1 100.00
csr_aliasing 1 1 100.00
gpio_csr_aliasing 1.170s 58.847us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
gpio_csr_mem_rw_with_rand_reset 1.680s 77.994us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
gpio_csr_rw 1.020s 47.942us 5 5 100.00
gpio_csr_aliasing 1.170s 58.847us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
direct_and_masked_out 20 20 100.00
gpio_random_dout_din 1.850s 547.039us 10 10 100.00
gpio_random_dout_din_no_pullup_pulldown 1.450s 38.345us 10 10 100.00
out_in_regs_read_write 10 10 100.00
gpio_dout_din_regs_random_rw 1.310s 420.542us 10 10 100.00
gpio_interrupt_programming 10 10 100.00
gpio_intr_rand_pgm 1.670s 418.409us 10 10 100.00
random_interrupt_trigger 10 10 100.00
gpio_rand_intr_trigger 3.250s 207.221us 10 10 100.00
interrupt_and_noise_filter 10 10 100.00
gpio_intr_with_filter_rand_intr_event 3.530s 207.540us 10 10 100.00
noise_filter_stress 10 10 100.00
gpio_filter_stress 20.570s 350.636us 10 10 100.00
regs_long_reads_and_writes 10 10 100.00
gpio_random_long_reg_writes_reg_reads 6.010s 2260.300us 10 10 100.00
full_random 10 10 100.00
gpio_full_random 1.340s 109.977us 10 10 100.00
stress_all 2 10 20.00
gpio_stress_all 78.600s 6138.231us 2 10 20.00
alert_test 10 10 100.00
gpio_alert_test 0.920s 21.002us 10 10 100.00
intr_test 10 10 100.00
gpio_intr_test 0.970s 18.768us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
gpio_tl_errors 3.160s 108.664us 25 25 100.00
tl_d_illegal_access 25 25 100.00
gpio_tl_errors 3.160s 108.664us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
gpio_csr_rw 1.020s 47.942us 5 5 100.00
gpio_same_csr_outstanding 1.110s 135.563us 5 5 100.00
gpio_csr_aliasing 1.170s 58.847us 1 1 100.00
gpio_csr_hw_reset 0.990s 67.024us 1 1 100.00
tl_d_partial_access 12 12 100.00
gpio_csr_rw 1.020s 47.942us 5 5 100.00
gpio_same_csr_outstanding 1.110s 135.563us 5 5 100.00
gpio_csr_aliasing 1.170s 58.847us 1 1 100.00
gpio_csr_hw_reset 0.990s 67.024us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
gpio_tl_intg_err 1.850s 152.053us 25 25 100.00
gpio_sec_cm 1.250s 74.083us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
gpio_tl_intg_err 1.850s 152.053us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
straps_data 7 10 70.00
gpio_rand_straps 0.920s 45.262us 7 10 70.00
stress_all_with_rand_reset 0 10 0.00
gpio_stress_all_with_rand_reset 8.830s 768.802us 0 10 0.00

Error Messages

   Test seed line log context
UVM_ERROR (gpio_scoreboard.sv:216) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 11 test runs
gpio_stress_all 54031979519563993218539759375029127904102510507636028154840378385353403169630 77
UVM_INFO @ 779858566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 81952878218440640470573097999215568105142947445977663348563624687976567765628 75
UVM_INFO @ 2816147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 79731878722416317622274789970783192756631154267292214444696506370998943180201 483
UVM_INFO @ 2119573960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 94361319611448634676983692880561114845618105938842075219273398548919188041493 75
UVM_INFO @ 4680565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 35110140965285224802722322609000375925934789427776301233689703654287064614092 434
UVM_INFO @ 870830792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 6896946010036055408009823677660857046356875323197845774594727802445578449356 75
UVM_INFO @ 1381180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 8769321370830728413514986570803465744117969841913297494816107058579460031355 867
UVM_INFO @ 2799160280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 82562969678685008899638110735564549479291098634248389987827727741342604563053 581
UVM_INFO @ 35060707202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 15543008233897998999319932662080642006823412200893957158290734433786649478924 630
UVM_INFO @ 1155003957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 37992854616467703465779280877499346884591162860969339560437861421561123927154 704
UVM_INFO @ 11016298969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 43328875250965465858305621003268957397334889312308377722748430983189043403175 76
UVM_INFO @ 610969455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [gpio_common_vseq] Check failed (vseq_done) 5 test runs
gpio_stress_all_with_rand_reset 28118568880878549770950381447915813641703406163929291858062772303425016556134 80
UVM_INFO @ 3853886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 17870932697393798226824753610318516968293389624888559612413545068436499738317 169
UVM_INFO @ 768801885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 107033328488920625276949544062544844620832786580349670756276437455373641552189 80
UVM_INFO @ 3299491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 74737834460999067814459845284565539473756430331699512959335552548032142576854 297
UVM_INFO @ 563821233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 22755525211082467437621977946950694531239084802266430453525589735227436495562 80
UVM_INFO @ 16944434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* 5 test runs
gpio_stress_all_with_rand_reset 78909019385502586111324844567548883402828731341955304984085085840619974929697 140
UVM_INFO @ 1340112377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 113104524731241842416825220741146978647839212337075195090485024191561288363477 78
UVM_INFO @ 5458862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 101361133833586284261613949173349904089781166884034190040825608859738033146123 82
UVM_INFO @ 2446827583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 88735808144914385766329242023630922130689656568919191231081045684211504597573 78
UVM_INFO @ 6820986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 104343101269901609277542983680119231439269731565507704236138239214267295201965 79
UVM_INFO @ 180450869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---