Simulation Results: hmac

 
13/06/2026 02:15:06 DVSim: v1.49.0 sha: 9424e63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.63 %
  • code
  • 98.60 %
  • assert
  • 97.60 %
  • func
  • 99.68 %
  • line
  • 99.74 %
  • branch
  • 99.67 %
  • cond
  • 96.52 %
  • toggle
  • 100.00 %
  • FSM
  • 97.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 15.300s 6599.897us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.770s 15.017us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 1.190s 66.195us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 8.130s 636.324us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.540s 423.706us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 714.250s 270213.197us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 1.190s 66.195us 5 5 100.00
hmac_csr_aliasing 3.540s 423.706us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 127.310s 21071.212us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 115.670s 12288.742us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 282.070s 21024.642us 30 30 100.00
hmac_test_sha384_vectors 575.090s 21422.766us 75 75 100.00
hmac_test_sha512_vectors 523.500s 80291.631us 75 75 100.00
hmac_test_hmac256_vectors 14.730s 826.235us 50 50 100.00
hmac_test_hmac384_vectors 16.870s 3814.037us 60 60 100.00
hmac_test_hmac512_vectors 18.330s 4817.422us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 35.900s 4939.478us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1088.520s 35143.701us 10 10 100.00
error 10 10 100.00
hmac_error 111.400s 53404.623us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 96.000s 24008.159us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 15.300s 6599.897us 10 10 100.00
hmac_long_msg 127.310s 21071.212us 10 10 100.00
hmac_back_pressure 115.670s 12288.742us 25 25 100.00
hmac_datapath_stress 1088.520s 35143.701us 10 10 100.00
hmac_burst_wr 35.900s 4939.478us 50 50 100.00
hmac_stress_all 3034.010s 86472.648us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 15.300s 6599.897us 10 10 100.00
hmac_long_msg 127.310s 21071.212us 10 10 100.00
hmac_back_pressure 115.670s 12288.742us 25 25 100.00
hmac_datapath_stress 1088.520s 35143.701us 10 10 100.00
hmac_wipe_secret 96.000s 24008.159us 10 10 100.00
hmac_test_sha256_vectors 282.070s 21024.642us 30 30 100.00
hmac_test_sha384_vectors 575.090s 21422.766us 75 75 100.00
hmac_test_sha512_vectors 523.500s 80291.631us 75 75 100.00
hmac_test_hmac256_vectors 14.730s 826.235us 50 50 100.00
hmac_test_hmac384_vectors 16.870s 3814.037us 60 60 100.00
hmac_test_hmac512_vectors 18.330s 4817.422us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 15.300s 6599.897us 10 10 100.00
hmac_long_msg 127.310s 21071.212us 10 10 100.00
hmac_back_pressure 115.670s 12288.742us 25 25 100.00
hmac_datapath_stress 1088.520s 35143.701us 10 10 100.00
hmac_burst_wr 35.900s 4939.478us 50 50 100.00
hmac_error 111.400s 53404.623us 10 10 100.00
hmac_wipe_secret 96.000s 24008.159us 10 10 100.00
hmac_test_sha256_vectors 282.070s 21024.642us 30 30 100.00
hmac_test_sha384_vectors 575.090s 21422.766us 75 75 100.00
hmac_test_sha512_vectors 523.500s 80291.631us 75 75 100.00
hmac_test_hmac256_vectors 14.730s 826.235us 50 50 100.00
hmac_test_hmac384_vectors 16.870s 3814.037us 60 60 100.00
hmac_test_hmac512_vectors 18.330s 4817.422us 75 75 100.00
hmac_stress_all 3034.010s 86472.648us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 3034.010s 86472.648us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 0.920s 22.659us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 0.940s 21.684us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 4.730s 501.869us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 4.730s 501.869us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 0.770s 15.017us 1 1 100.00
hmac_csr_rw 1.190s 66.195us 5 5 100.00
hmac_csr_aliasing 3.540s 423.706us 1 1 100.00
hmac_same_csr_outstanding 2.170s 92.773us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 0.770s 15.017us 1 1 100.00
hmac_csr_rw 1.190s 66.195us 5 5 100.00
hmac_csr_aliasing 3.540s 423.706us 1 1 100.00
hmac_same_csr_outstanding 2.170s 92.773us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 1.270s 96.861us 5 5 100.00
hmac_tl_intg_err 5.080s 1096.494us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 5.080s 1096.494us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 15.300s 6599.897us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 7.950s 627.129us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 859.150s 98349.989us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.980s 186.860us 1 1 100.00