Simulation Results: keymgr

 
13/06/2026 02:15:06 DVSim: v1.49.0 sha: 9424e63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.73 %
  • code
  • 98.28 %
  • assert
  • 97.72 %
  • func
  • 91.18 %
  • line
  • 99.16 %
  • branch
  • 98.90 %
  • cond
  • 98.04 %
  • toggle
  • 97.61 %
  • FSM
  • 97.67 %
Validation stages
V1
100.00%
V2
99.06%
V2S
100.00%
V3
55.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 30 30 100.00
keymgr_smoke 19.040s 982.925us 30 30 100.00
random 30 30 100.00
keymgr_random 42.250s 1998.827us 30 30 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.360s 83.289us 1 1 100.00
csr_rw 5 5 100.00
keymgr_csr_rw 1.560s 36.728us 5 5 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 9.670s 1540.687us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 3.220s 138.960us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
keymgr_csr_mem_rw_with_rand_reset 1.740s 96.196us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
keymgr_csr_rw 1.560s 36.728us 5 5 100.00
keymgr_csr_aliasing 3.220s 138.960us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 61.960s 3947.378us 50 50 100.00
sideload 80 80 100.00
keymgr_sideload 30.240s 2649.438us 20 20 100.00
keymgr_sideload_kmac 18.800s 2940.954us 20 20 100.00
keymgr_sideload_aes 26.910s 1471.616us 20 20 100.00
keymgr_sideload_otbn 23.380s 2991.954us 20 20 100.00
direct_to_disabled_state 30 30 100.00
keymgr_direct_to_disabled 14.950s 1612.430us 30 30 100.00
lc_disable 50 50 100.00
keymgr_lc_disable 11.370s 582.307us 50 50 100.00
kmac_error_response 20 20 100.00
keymgr_kmac_rsp_err 5.290s 558.195us 20 20 100.00
invalid_sw_input 20 20 100.00
keymgr_sw_invalid_input 36.380s 1985.343us 20 20 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 37.240s 10787.976us 50 50 100.00
sync_async_fault_cross 20 20 100.00
keymgr_sync_async_fault_cross 9.570s 2102.417us 20 20 100.00
stress_all 46 50 92.00
keymgr_stress_all 258.940s 17584.234us 46 50 92.00
intr_test 10 10 100.00
keymgr_intr_test 1.150s 10.703us 10 10 100.00
alert_test 10 10 100.00
keymgr_alert_test 1.160s 12.116us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
keymgr_tl_errors 5.920s 170.367us 25 25 100.00
tl_d_illegal_access 25 25 100.00
keymgr_tl_errors 5.920s 170.367us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
keymgr_csr_hw_reset 1.360s 83.289us 1 1 100.00
keymgr_csr_rw 1.560s 36.728us 5 5 100.00
keymgr_csr_aliasing 3.220s 138.960us 1 1 100.00
keymgr_same_csr_outstanding 3.060s 941.902us 5 5 100.00
tl_d_partial_access 12 12 100.00
keymgr_csr_hw_reset 1.360s 83.289us 1 1 100.00
keymgr_csr_rw 1.560s 36.728us 5 5 100.00
keymgr_csr_aliasing 3.220s 138.960us 1 1 100.00
keymgr_same_csr_outstanding 3.060s 941.902us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 13.120s 1380.446us 5 5 100.00
tl_intg_err 30 30 100.00
keymgr_sec_cm 13.120s 1380.446us 5 5 100.00
keymgr_tl_intg_err 8.810s 267.663us 25 25 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 6.730s 880.436us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 6.730s 880.436us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 6.730s 880.436us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 6.730s 880.436us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 14.400s 840.487us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 13.120s 1380.446us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 13.120s 1380.446us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
keymgr_tl_intg_err 8.810s 267.663us 25 25 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 6.730s 880.436us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 61.960s 3947.378us 50 50 100.00
sec_cm_reseed_config_regwen 35 35 100.00
keymgr_random 42.250s 1998.827us 30 30 100.00
keymgr_csr_rw 1.560s 36.728us 5 5 100.00
sec_cm_sw_binding_config_regwen 35 35 100.00
keymgr_random 42.250s 1998.827us 30 30 100.00
keymgr_csr_rw 1.560s 36.728us 5 5 100.00
sec_cm_max_key_ver_config_regwen 35 35 100.00
keymgr_random 42.250s 1998.827us 30 30 100.00
keymgr_csr_rw 1.560s 36.728us 5 5 100.00
sec_cm_lc_ctrl_intersig_mubi 50 50 100.00
keymgr_lc_disable 11.370s 582.307us 50 50 100.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 37.240s 10787.976us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 37.240s 10787.976us 50 50 100.00
sec_cm_hw_key_sw_noaccess 30 30 100.00
keymgr_random 42.250s 1998.827us 30 30 100.00
sec_cm_output_keys_ctrl_redun 20 20 100.00
keymgr_sideload_protect 17.630s 1827.279us 20 20 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 13.120s 1380.446us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 13.120s 1380.446us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 13.120s 1380.446us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 13.730s 7095.342us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 50 50 100.00
keymgr_lc_disable 11.370s 582.307us 50 50 100.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 13.120s 1380.446us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 13.120s 1380.446us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 13.120s 1380.446us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 13.730s 7095.342us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 13.730s 7095.342us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 13.120s 1380.446us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 13.730s 7095.342us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 13.120s 1380.446us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 13.730s 7095.342us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 11 20 55.00
keymgr_stress_all_with_rand_reset 21.880s 664.575us 11 20 55.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 8 test runs
keymgr_stress_all_with_rand_reset 70632885436198205028656390265371260879968213848435983770718922792893287244683 294
UVM_INFO @ 466878790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 108723260307900611596012618596152484951494065680227979328219636038347748824699 178
UVM_INFO @ 118438503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 19533227244782782010792731678950468958024722756107171538763950528735236057426 399
UVM_INFO @ 1111944305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 38623947464113387257531126193668996316646258640142181517369241642371598095459 1772
UVM_INFO @ 2944578392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 11661591191125755386595869205588179392675432278893085284077245854408438614675 313
UVM_INFO @ 781730856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 56558010662794587317613023921893294551034574164016770568613382399856529060390 402
UVM_INFO @ 367867192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 99904815909510254079884759167756712856635610124466806038397174891315176273229 276
UVM_INFO @ 138091630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 12552196412922181539226586981650173393827360005430997572943860282839591628610 1868
UVM_INFO @ 664574724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* 2 test runs
keymgr_stress_all 107697125290976520369672142904718299845536709405883521559556298263157368865013 3255
UVM_INFO @ 4188881511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 63728214603760055490258651439294181375708157045796791226398730423729552409251 402
UVM_INFO @ 100562429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share0_output_* 1 test run
keymgr_stress_all 71073619612326334617656104752955571844155361689479465429435391401000164930136 2101
UVM_INFO @ 1799911737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StDisabled for Attestation Kmac 1 test run
keymgr_stress_all 73433414596062720275114263281297760975979887491843791615179530832208714610573 623
UVM_INFO @ 70718346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share1_output_* 1 test run
keymgr_stress_all 24052020622705560240722233813439500838511938671250770598661668854432599494191 960
UVM_INFO @ 1661565464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---