Simulation Results: lc_ctrl/volatile_unlock_disabled

 
13/06/2026 02:15:06 DVSim: v1.49.0 sha: 9424e63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.08 %
  • code
  • 85.86 %
  • assert
  • 94.13 %
  • func
  • 96.26 %
  • line
  • 97.28 %
  • branch
  • 94.00 %
  • cond
  • 81.55 %
  • toggle
  • 88.25 %
  • FSM
  • 68.22 %
Validation stages
V1
100.00%
V2
99.30%
V2S
100.00%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 5.260s 128.926us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.120s 89.229us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.380s 13.855us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.200s 123.813us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.540s 440.058us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.090s 384.952us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.380s 13.855us 5 5 100.00
lc_ctrl_csr_aliasing 1.540s 440.058us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 9.590s 257.285us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 11.720s 3038.645us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.360s 14.362us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 3.300s 226.868us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 16.420s 673.199us 20 20 100.00
lc_errors 19 20 95.00
lc_ctrl_errors 13.700s 1710.212us 19 20 95.00
security_escalation 137 140 97.86
lc_ctrl_state_failure 16.420s 673.199us 20 20 100.00
lc_ctrl_prog_failure 3.300s 226.868us 20 20 100.00
lc_ctrl_errors 13.700s 1710.212us 19 20 95.00
lc_ctrl_security_escalation 12.430s 1774.622us 20 20 100.00
lc_ctrl_jtag_state_failure 75.510s 5362.618us 20 20 100.00
lc_ctrl_jtag_prog_failure 20.200s 785.138us 20 20 100.00
lc_ctrl_jtag_errors 49.570s 1874.502us 18 20 90.00
jtag_access 208 210 99.05
lc_ctrl_jtag_smoke 10.210s 2487.035us 20 20 100.00
lc_ctrl_jtag_state_post_trans 26.760s 1128.834us 20 20 100.00
lc_ctrl_jtag_prog_failure 20.200s 785.138us 20 20 100.00
lc_ctrl_jtag_errors 49.570s 1874.502us 18 20 90.00
lc_ctrl_jtag_access 20.830s 3932.226us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 34.870s 1522.758us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.190s 1042.807us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.690s 312.198us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 22.670s 6377.237us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 19.440s 8657.577us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.190s 107.412us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.850s 477.961us 10 10 100.00
lc_ctrl_jtag_alert_test 2.420s 438.881us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 32.830s 1366.197us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.360s 42.942us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 267.650s 35486.428us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.810s 156.870us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 5.100s 172.118us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 5.100s 172.118us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.120s 89.229us 1 1 100.00
lc_ctrl_csr_rw 1.380s 13.855us 5 5 100.00
lc_ctrl_csr_aliasing 1.540s 440.058us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.610s 29.759us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.120s 89.229us 1 1 100.00
lc_ctrl_csr_rw 1.380s 13.855us 5 5 100.00
lc_ctrl_csr_aliasing 1.540s 440.058us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.610s 29.759us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 9.110s 146.899us 5 5 100.00
lc_ctrl_tl_intg_err 3.820s 519.527us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 3.820s 519.527us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 11.720s 3038.645us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 16.420s 673.199us 20 20 100.00
lc_ctrl_sec_cm 9.110s 146.899us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 16.420s 673.199us 20 20 100.00
lc_ctrl_sec_cm 9.110s 146.899us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 16.420s 673.199us 20 20 100.00
lc_ctrl_sec_cm 9.110s 146.899us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 16.420s 673.199us 20 20 100.00
lc_ctrl_sec_cm 9.110s 146.899us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 16.420s 673.199us 20 20 100.00
lc_ctrl_sec_cm 9.110s 146.899us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 16.420s 673.199us 20 20 100.00
lc_ctrl_sec_cm 9.110s 146.899us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 16.420s 673.199us 20 20 100.00
lc_ctrl_sec_cm 9.110s 146.899us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 16.420s 673.199us 20 20 100.00
lc_ctrl_sec_cm 9.110s 146.899us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 12.430s 1774.622us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 9.590s 257.285us 20 20 100.00
lc_ctrl_jtag_state_post_trans 26.760s 1128.834us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 20.240s 675.622us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 20.240s 675.622us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 11.790s 1374.792us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 9.640s 3649.999us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 9.640s 3649.999us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 10 70.00
lc_ctrl_stress_all_with_rand_reset 106.670s 6100.581us 7 10 70.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
lc_ctrl_stress_all_with_rand_reset 1548400510883189906163145159865597086496870660634462362362019103353225746695 4681
UVM_INFO @ 4621305072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 4791435731546405929714091453234711038123918949008244725889927977706713644986 11058
UVM_INFO @ 19328711277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 29221625555673146494035204432557202896339546423196429465290237394817640974001 6528
UVM_INFO @ 6551879126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 3 test runs
lc_ctrl_jtag_errors 96844621621818467306573535793819211907232507110562472070790545667125958839 1020
UVM_INFO @ 949618818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 62868584217001926093040635161303015019302321492414368450924213900851065506141 468
UVM_INFO @ 1136807916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 36492611305265107293624062666602888587068461248377381871132810702083256176644 1358
UVM_INFO @ 720016724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---