Simulation Results: lc_ctrl/volatile_unlock_enabled

 
13/06/2026 02:15:06 DVSim: v1.49.0 sha: 9424e63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.31 %
  • code
  • 86.02 %
  • assert
  • 94.83 %
  • func
  • 96.09 %
  • line
  • 97.26 %
  • branch
  • 93.80 %
  • cond
  • 81.62 %
  • toggle
  • 88.25 %
  • FSM
  • 69.16 %
Validation stages
V1
100.00%
V2
99.53%
V2S
100.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 6.950s 597.481us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.310s 28.456us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.370s 22.264us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.770s 24.667us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.180s 141.842us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.730s 94.766us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.370s 22.264us 5 5 100.00
lc_ctrl_csr_aliasing 2.180s 141.842us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 8.740s 59.793us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 14.480s 433.604us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.250s 14.043us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 3.810s 538.664us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 12.640s 392.106us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 11.330s 1150.508us 20 20 100.00
security_escalation 140 140 100.00
lc_ctrl_state_failure 12.640s 392.106us 20 20 100.00
lc_ctrl_prog_failure 3.810s 538.664us 20 20 100.00
lc_ctrl_errors 11.330s 1150.508us 20 20 100.00
lc_ctrl_security_escalation 13.340s 424.688us 20 20 100.00
lc_ctrl_jtag_state_failure 69.470s 16704.913us 20 20 100.00
lc_ctrl_jtag_prog_failure 16.580s 3051.081us 20 20 100.00
lc_ctrl_jtag_errors 77.420s 12511.176us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 10.140s 327.106us 20 20 100.00
lc_ctrl_jtag_state_post_trans 29.350s 24645.366us 20 20 100.00
lc_ctrl_jtag_prog_failure 16.580s 3051.081us 20 20 100.00
lc_ctrl_jtag_errors 77.420s 12511.176us 20 20 100.00
lc_ctrl_jtag_access 18.170s 4266.988us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 21.070s 5320.299us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.060s 204.704us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.500s 170.794us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 22.750s 4399.133us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 6.790s 3814.740us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.920s 47.091us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.320s 3861.163us 10 10 100.00
lc_ctrl_jtag_alert_test 2.840s 106.371us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 22.020s 1366.539us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.400s 12.996us 10 10 100.00
stress_all 8 10 80.00
lc_ctrl_stress_all 294.340s 10686.516us 8 10 80.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.850s 69.134us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 7.000s 192.149us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 7.000s 192.149us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.310s 28.456us 1 1 100.00
lc_ctrl_csr_rw 1.370s 22.264us 5 5 100.00
lc_ctrl_csr_aliasing 2.180s 141.842us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.790s 48.795us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.310s 28.456us 1 1 100.00
lc_ctrl_csr_rw 1.370s 22.264us 5 5 100.00
lc_ctrl_csr_aliasing 2.180s 141.842us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.790s 48.795us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 9.330s 971.987us 5 5 100.00
lc_ctrl_tl_intg_err 3.170s 215.816us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 3.170s 215.816us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 14.480s 433.604us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 12.640s 392.106us 20 20 100.00
lc_ctrl_sec_cm 9.330s 971.987us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 12.640s 392.106us 20 20 100.00
lc_ctrl_sec_cm 9.330s 971.987us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 12.640s 392.106us 20 20 100.00
lc_ctrl_sec_cm 9.330s 971.987us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 12.640s 392.106us 20 20 100.00
lc_ctrl_sec_cm 9.330s 971.987us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 12.640s 392.106us 20 20 100.00
lc_ctrl_sec_cm 9.330s 971.987us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 12.640s 392.106us 20 20 100.00
lc_ctrl_sec_cm 9.330s 971.987us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 12.640s 392.106us 20 20 100.00
lc_ctrl_sec_cm 9.330s 971.987us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 12.640s 392.106us 20 20 100.00
lc_ctrl_sec_cm 9.330s 971.987us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 13.340s 424.688us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 8.740s 59.793us 20 20 100.00
lc_ctrl_jtag_state_post_trans 29.350s 24645.366us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 15.900s 648.874us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 15.900s 648.874us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 10.950s 604.821us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 16.370s 2002.087us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 16.370s 2002.087us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
lc_ctrl_stress_all_with_rand_reset 96.820s 7234.999us 4 10 40.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
lc_ctrl_stress_all_with_rand_reset 42607245602089236051384156978979713549518010043572744125501633190965415708639 165
UVM_INFO @ 3254184627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 47704939662914879728520541780793103503260457301689959735439260272984070800212 7026
UVM_INFO @ 3931798324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 15243639482236780841354463257647491058135772112002833572531694693167216455225 673
UVM_INFO @ 2428383313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 24805375742834396553676172401972055854625363033480287289228129834729420602291 957
UVM_INFO @ 1252468167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:923) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 2 test runs
lc_ctrl_stress_all_with_rand_reset 59680311463038300761230301152732300163969205241693666998233852930214874089662 5090
UVM_INFO @ 3728893759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 7549798134927241825104369047099293317866950386889423406778645788002810466308 2424
UVM_INFO @ 3185150834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 2 test runs
lc_ctrl_stress_all 3110906740063212161442193596087368559032617480601531723838181161451847845846 3548
UVM_INFO @ 9533557941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 58541252644339528223109506740668069111536478260038552375211401894870194903338 13792
UVM_INFO @ 80663677476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---