Simulation Results

Simulation Results: otbn

13/06/2026 02:15:06 DVSim: v1.49.0 sha: 9424e63 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
98.16 %

code
96.78 %

assert
97.69 %

func
100.00 %

block
99.53 %

line
99.64 %

branch
93.99 %

toggle
93.49 %

FSM
100.00 %

Validation stages

V1		99.14%
V2		98.16%
V2S		97.57%
V3		20.00%
unmapped		100.00%

115/116 passed

99.14 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	otbn_smoke	42.000s	336.281us	1	1	100.00
single_binary				99	100	99.00
	otbn_single	57.000s	806.021us	99	100	99.00
csr_hw_reset				1	1	100.00
	otbn_csr_hw_reset	39.000s	23.507us	1	1	100.00
csr_rw				5	5	100.00
	otbn_csr_rw	39.000s	14.458us	5	5	100.00
csr_bit_bash				1	1	100.00
	otbn_csr_bit_bash	44.000s	172.809us	1	1	100.00
csr_aliasing				1	1	100.00
	otbn_csr_aliasing	39.000s	49.117us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	otbn_csr_mem_rw_with_rand_reset	41.000s	24.968us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	otbn_csr_rw	39.000s	14.458us	5	5	100.00
	otbn_csr_aliasing	39.000s	49.117us	1	1	100.00
mem_walk				1	1	100.00
	otbn_mem_walk	174.000s	80652.121us	1	1	100.00
mem_partial_access				1	1	100.00
	otbn_mem_partial_access	61.000s	327.680us	1	1	100.00

160/163 passed

98.16 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
reset_recovery				9	10	90.00
	otbn_reset	297.000s	1118.667us	9	10	90.00
multi_error				1	1	100.00
	otbn_multi_err	79.000s	672.419us	1	1	100.00
back_to_back				9	10	90.00
	otbn_multi	120.000s	477.117us	9	10	90.00
stress_all				10	10	100.00
	otbn_stress_all	154.000s	556.831us	10	10	100.00
lc_escalation				59	60	98.33
	otbn_escalate	41.000s	276.148us	59	60	98.33
zero_state_err_urnd				5	5	100.00
	otbn_zero_state_err_urnd	18.000s	20.845us	5	5	100.00
sw_errs_fatal_chk				10	10	100.00
	otbn_sw_errs_fatal_chk	43.000s	187.393us	10	10	100.00
alert_test				10	10	100.00
	otbn_alert_test	40.000s	24.646us	10	10	100.00
intr_test				10	10	100.00
	otbn_intr_test	40.000s	52.338us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	otbn_tl_errors	22.000s	361.925us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	otbn_tl_errors	22.000s	361.925us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	otbn_csr_hw_reset	39.000s	23.507us	1	1	100.00
	otbn_csr_rw	39.000s	14.458us	5	5	100.00
	otbn_csr_aliasing	39.000s	49.117us	1	1	100.00
	otbn_same_csr_outstanding	39.000s	31.825us	5	5	100.00
tl_d_partial_access				12	12	100.00
	otbn_csr_hw_reset	39.000s	23.507us	1	1	100.00
	otbn_csr_rw	39.000s	14.458us	5	5	100.00
	otbn_csr_aliasing	39.000s	49.117us	1	1	100.00
	otbn_same_csr_outstanding	39.000s	31.825us	5	5	100.00

V2S

321/329 passed

97.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
mem_integrity				25	25	100.00
	otbn_imem_err	41.000s	38.623us	10	10	100.00
	otbn_dmem_err	40.000s	60.809us	15	15	100.00
internal_integrity				16	17	94.12
	otbn_alu_bignum_mod_err	44.000s	36.221us	5	5	100.00
	otbn_controller_ispr_rdata_err	41.000s	35.243us	4	5	80.00
	otbn_mac_bignum_acc_err	43.000s	78.308us	5	5	100.00
	otbn_urnd_err	23.000s	34.675us	2	2	100.00
illegal_bus_access				5	5	100.00
	otbn_illegal_mem_acc	38.000s	30.142us	5	5	100.00
otbn_mem_gnt_acc_err				2	2	100.00
	otbn_mem_gnt_acc_err	42.000s	39.744us	2	2	100.00
otbn_non_sec_partial_wipe				10	10	100.00
	otbn_partial_wipe	39.000s	29.234us	10	10	100.00
tl_intg_err				30	30	100.00
	otbn_sec_cm	320.000s	2409.636us	5	5	100.00
	otbn_tl_intg_err	59.000s	340.989us	25	25	100.00
passthru_mem_tl_intg_err				4	5	80.00
	otbn_passthru_mem_tl_intg_err	87.000s	180.369us	4	5	80.00
prim_fsm_check				5	5	100.00
	otbn_sec_cm	320.000s	2409.636us	5	5	100.00
prim_count_check				5	5	100.00
	otbn_sec_cm	320.000s	2409.636us	5	5	100.00
sec_cm_mem_scramble				1	1	100.00
	otbn_smoke	42.000s	336.281us	1	1	100.00
sec_cm_data_mem_integrity				15	15	100.00
	otbn_dmem_err	40.000s	60.809us	15	15	100.00
sec_cm_instruction_mem_integrity				10	10	100.00
	otbn_imem_err	41.000s	38.623us	10	10	100.00
sec_cm_bus_integrity				25	25	100.00
	otbn_tl_intg_err	59.000s	340.989us	25	25	100.00
sec_cm_controller_fsm_global_esc				59	60	98.33
	otbn_escalate	41.000s	276.148us	59	60	98.33
sec_cm_controller_fsm_local_esc				40	40	100.00
	otbn_imem_err	41.000s	38.623us	10	10	100.00
	otbn_dmem_err	40.000s	60.809us	15	15	100.00
	otbn_zero_state_err_urnd	18.000s	20.845us	5	5	100.00
	otbn_illegal_mem_acc	38.000s	30.142us	5	5	100.00
	otbn_sec_cm	320.000s	2409.636us	5	5	100.00
sec_cm_controller_fsm_sparse				5	5	100.00
	otbn_sec_cm	320.000s	2409.636us	5	5	100.00
sec_cm_scramble_key_sideload				99	100	99.00
	otbn_single	57.000s	806.021us	99	100	99.00
sec_cm_scramble_ctrl_fsm_local_esc				40	40	100.00
	otbn_imem_err	41.000s	38.623us	10	10	100.00
	otbn_dmem_err	40.000s	60.809us	15	15	100.00
	otbn_zero_state_err_urnd	18.000s	20.845us	5	5	100.00
	otbn_illegal_mem_acc	38.000s	30.142us	5	5	100.00
	otbn_sec_cm	320.000s	2409.636us	5	5	100.00
sec_cm_scramble_ctrl_fsm_sparse				5	5	100.00
	otbn_sec_cm	320.000s	2409.636us	5	5	100.00
sec_cm_start_stop_ctrl_fsm_global_esc				59	60	98.33
	otbn_escalate	41.000s	276.148us	59	60	98.33
sec_cm_start_stop_ctrl_fsm_local_esc				40	40	100.00
	otbn_imem_err	41.000s	38.623us	10	10	100.00
	otbn_dmem_err	40.000s	60.809us	15	15	100.00
	otbn_zero_state_err_urnd	18.000s	20.845us	5	5	100.00
	otbn_illegal_mem_acc	38.000s	30.142us	5	5	100.00
	otbn_sec_cm	320.000s	2409.636us	5	5	100.00
sec_cm_start_stop_ctrl_fsm_sparse				5	5	100.00
	otbn_sec_cm	320.000s	2409.636us	5	5	100.00
sec_cm_data_reg_sw_sca				99	100	99.00
	otbn_single	57.000s	806.021us	99	100	99.00
sec_cm_ctrl_redun				12	12	100.00
	otbn_ctrl_redun	37.000s	73.195us	12	12	100.00
sec_cm_pc_ctrl_flow_redun				5	5	100.00
	otbn_pc_ctrl_flow_redun	40.000s	57.251us	5	5	100.00
sec_cm_rnd_bus_consistency				4	5	80.00
	otbn_rnd_sec_cm	104.000s	228.575us	4	5	80.00
sec_cm_rnd_rng_digest				4	5	80.00
	otbn_rnd_sec_cm	104.000s	228.575us	4	5	80.00
sec_cm_rf_base_data_reg_sw_integrity				9	10	90.00
	otbn_rf_base_intg_err	41.000s	29.744us	9	10	90.00
sec_cm_rf_base_data_reg_sw_glitch_detect				5	5	100.00
	otbn_sec_cm	320.000s	2409.636us	5	5	100.00
sec_cm_stack_wr_ptr_ctr_redun				5	5	100.00
	otbn_sec_cm	320.000s	2409.636us	5	5	100.00
sec_cm_rf_bignum_data_reg_sw_integrity				9	10	90.00
	otbn_rf_bignum_intg_err	41.000s	196.836us	9	10	90.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect				5	5	100.00
	otbn_sec_cm	320.000s	2409.636us	5	5	100.00
sec_cm_loop_stack_ctr_redun				5	5	100.00
	otbn_sec_cm	320.000s	2409.636us	5	5	100.00
sec_cm_loop_stack_addr_integrity				5	5	100.00
	otbn_stack_addr_integ_chk	36.000s	43.661us	5	5	100.00
sec_cm_call_stack_addr_integrity				5	5	100.00
	otbn_stack_addr_integ_chk	36.000s	43.661us	5	5	100.00
sec_cm_start_stop_ctrl_state_consistency				7	7	100.00
	otbn_sec_wipe_err	36.000s	10.273us	7	7	100.00
sec_cm_data_mem_sec_wipe				99	100	99.00
	otbn_single	57.000s	806.021us	99	100	99.00
sec_cm_instruction_mem_sec_wipe				99	100	99.00
	otbn_single	57.000s	806.021us	99	100	99.00
sec_cm_data_reg_sw_sec_wipe				99	100	99.00
	otbn_single	57.000s	806.021us	99	100	99.00
sec_cm_write_mem_integrity				9	10	90.00
	otbn_multi	120.000s	477.117us	9	10	90.00
sec_cm_ctrl_flow_count				99	100	99.00
	otbn_single	57.000s	806.021us	99	100	99.00
sec_cm_ctrl_flow_sca				99	100	99.00
	otbn_single	57.000s	806.021us	99	100	99.00
sec_cm_data_mem_sw_noaccess				5	5	100.00
	otbn_sw_no_acc	34.000s	22.509us	5	5	100.00
sec_cm_key_sideload				99	100	99.00
	otbn_single	57.000s	806.021us	99	100	99.00
sec_cm_tlul_fifo_ctr_redun				5	5	100.00
	otbn_sec_cm	320.000s	2409.636us	5	5	100.00

2/10 passed

20.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				2	10	20.00
	otbn_stress_all_with_rand_reset	540.000s	8968.464us	2	10	20.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	otbn_smoke_vectorized	36.000s	19.399us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				7 test runs
	otbn_stress_all_with_rand_reset	54756500123072345191640538347558496949302976176998413662142055231144138044903	428	UVM_INFO @ 2030417805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	74214992788945069780708985001544962895712090509013449285737161260693581673104	265	UVM_INFO @ 2206911198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	66859366087291685173683604695438667373350118935485543224128369942914586064672	419	UVM_INFO @ 1914861172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	109785586360724805134952482366265491335955169209422265889093757185190303914780	495	UVM_INFO @ 13755496543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	73076404292728034304345387875569431945263750775682649487116698164005719030332	170	UVM_INFO @ 341556096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	99053817236405981660074055994487435735178907913682366749032855392277701900148	156	UVM_INFO @ 406994451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	2147213035575025671922060812030200999948562895763767355008012296155353024791	236	UVM_INFO @ 682381095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				3 test runs
	otbn_reset	67033055386961848664527201114365338319393028904250646294477636705849458556941	None	~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program) ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize assert bodysize is not None ^^^^^^^^^^^^^^^^^^^^ AssertionError ninja: build stopped: subcommand failed. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
	otbn_multi	108197602028280506842815934870905724792565832459697529602849051575170479593117	None	~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program) ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize assert bodysize is not None ^^^^^^^^^^^^^^^^^^^^ AssertionError ninja: build stopped: subcommand failed. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
	otbn_stress_all_with_rand_reset	66620308828802830677115536704713439229812246871109588758691736176739704698973	None	~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program) ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize assert bodysize is not None ^^^^^^^^^^^^^^^^^^^^ AssertionError ninja: build stopped: subcommand failed. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.				3 test runs
	otbn_passthru_mem_tl_intg_err	66561452099468280543033219920767802038844486890574250862530226894712638791031	96	UVM_INFO @ 63999240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_rnd_sec_cm	60698906423552686077512838734648295275658390139559935630713312167548668667361	137	UVM_INFO @ 228574558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_single	27397613094835667875752441768170959646617686680824237041380746956179093271105	112	UVM_INFO @ 118963549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error				3 test runs
	otbn_controller_ispr_rdata_err	58225705817118087892498023910709935852106515395945346868266843804695258060684	111	UVM_INFO @ 42211670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_rf_base_intg_err	8225931571815992968661104128804424994894009956976452900006720211920655792695	130	UVM_INFO @ 601259097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_rf_bignum_intg_err	54337829522055765017785685167124339155143267184574770790909680411073339124893	114	UVM_INFO @ 23814640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed				1 test run
	otbn_escalate	16423897802172632964573204953925390777933650604504029143525237806766202946379	112	UVM_ERROR @ 18336979 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A UVM_INFO @ 18336979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---