Simulation Results: otp_ctrl

 
13/06/2026 02:15:06 DVSim: v1.49.0 sha: 9424e63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.22 %
  • code
  • 85.98 %
  • assert
  • 95.46 %
  • func
  • 92.23 %
  • line
  • 90.25 %
  • branch
  • 86.75 %
  • cond
  • 94.02 %
  • toggle
  • 95.85 %
  • FSM
  • 63.02 %
Validation stages
V1
92.31%
V2
96.81%
V2S
96.67%
V3
30.69%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.690s 55.387us 1 1 100.00
smoke 10 10 100.00
otp_ctrl_smoke 17.740s 9819.986us 10 10 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.370s 183.664us 1 1 100.00
csr_rw 5 5 100.00
otp_ctrl_csr_rw 2.120s 601.668us 5 5 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 3.700s 210.302us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.170s 77.804us 1 1 100.00
csr_mem_rw_with_rand_reset 3 5 60.00
otp_ctrl_csr_mem_rw_with_rand_reset 22.070s 10101.459us 3 5 60.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otp_ctrl_csr_rw 2.120s 601.668us 5 5 100.00
otp_ctrl_csr_aliasing 4.170s 77.804us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.490s 145.467us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.330s 68.569us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 24.120s 13579.976us 1 1 100.00
init_fail 300 300 100.00
otp_ctrl_init_fail 7.980s 2803.648us 300 300 100.00
partition_check 43 60 71.67
otp_ctrl_background_chks 48.940s 9951.492us 10 10 100.00
otp_ctrl_check_fail 25.620s 3239.031us 33 50 66.00
regwen_during_otp_init 30 30 100.00
otp_ctrl_regwen 10.630s 1539.325us 30 30 100.00
partition_lock 30 30 100.00
otp_ctrl_dai_lock 43.920s 17276.646us 30 30 100.00
interface_key_check 10 10 100.00
otp_ctrl_parallel_key_req 21.730s 2985.583us 10 10 100.00
lc_interactions 209 210 99.52
otp_ctrl_parallel_lc_req 17.730s 950.971us 10 10 100.00
otp_ctrl_parallel_lc_esc 34.730s 15838.773us 199 200 99.50
otp_dai_errors 23 25 92.00
otp_ctrl_dai_errs 62.050s 28539.309us 23 25 92.00
otp_macro_errors 6 10 60.00
otp_ctrl_macro_errs 28.700s 4778.425us 6 10 60.00
test_access 10 10 100.00
otp_ctrl_test_access 25.700s 2170.540us 10 10 100.00
stress_all 10 10 100.00
otp_ctrl_stress_all 229.330s 106659.786us 10 10 100.00
intr_test 10 10 100.00
otp_ctrl_intr_test 2.170s 560.645us 10 10 100.00
alert_test 10 10 100.00
otp_ctrl_alert_test 2.460s 839.293us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otp_ctrl_tl_errors 6.510s 2606.886us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otp_ctrl_tl_errors 6.510s 2606.886us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otp_ctrl_csr_hw_reset 2.370s 183.664us 1 1 100.00
otp_ctrl_csr_rw 2.120s 601.668us 5 5 100.00
otp_ctrl_csr_aliasing 4.170s 77.804us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.760s 170.592us 5 5 100.00
tl_d_partial_access 12 12 100.00
otp_ctrl_csr_hw_reset 2.370s 183.664us 1 1 100.00
otp_ctrl_csr_rw 2.120s 601.668us 5 5 100.00
otp_ctrl_csr_aliasing 4.170s 77.804us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.760s 170.592us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
otp_ctrl_sec_cm 280.240s 157320.869us 5 5 100.00
tl_intg_err 30 30 100.00
otp_ctrl_sec_cm 280.240s 157320.869us 5 5 100.00
otp_ctrl_tl_intg_err 25.000s 20254.848us 25 25 100.00
prim_count_check 5 5 100.00
otp_ctrl_sec_cm 280.240s 157320.869us 5 5 100.00
prim_fsm_check 5 5 100.00
otp_ctrl_sec_cm 280.240s 157320.869us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
otp_ctrl_tl_intg_err 25.000s 20254.848us 25 25 100.00
sec_cm_secret_mem_scramble 10 10 100.00
otp_ctrl_smoke 17.740s 9819.986us 10 10 100.00
sec_cm_part_mem_digest 10 10 100.00
otp_ctrl_smoke 17.740s 9819.986us 10 10 100.00
sec_cm_dai_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 280.240s 157320.869us 5 5 100.00
sec_cm_kdi_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 280.240s 157320.869us 5 5 100.00
sec_cm_lci_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 280.240s 157320.869us 5 5 100.00
sec_cm_part_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 280.240s 157320.869us 5 5 100.00
sec_cm_scrmbl_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 280.240s 157320.869us 5 5 100.00
sec_cm_timer_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 280.240s 157320.869us 5 5 100.00
sec_cm_dai_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 280.240s 157320.869us 5 5 100.00
sec_cm_kdi_seed_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 280.240s 157320.869us 5 5 100.00
sec_cm_kdi_entropy_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 280.240s 157320.869us 5 5 100.00
sec_cm_lci_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 280.240s 157320.869us 5 5 100.00
sec_cm_part_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 280.240s 157320.869us 5 5 100.00
sec_cm_scrmbl_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 280.240s 157320.869us 5 5 100.00
sec_cm_timer_integ_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 280.240s 157320.869us 5 5 100.00
sec_cm_timer_cnsty_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 280.240s 157320.869us 5 5 100.00
sec_cm_timer_lfsr_redun 5 5 100.00
otp_ctrl_sec_cm 280.240s 157320.869us 5 5 100.00
sec_cm_dai_fsm_local_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 34.730s 15838.773us 199 200 99.50
otp_ctrl_sec_cm 280.240s 157320.869us 5 5 100.00
sec_cm_lci_fsm_local_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 34.730s 15838.773us 199 200 99.50
sec_cm_kdi_fsm_local_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 34.730s 15838.773us 199 200 99.50
sec_cm_part_fsm_local_esc 205 210 97.62
otp_ctrl_parallel_lc_esc 34.730s 15838.773us 199 200 99.50
otp_ctrl_macro_errs 28.700s 4778.425us 6 10 60.00
sec_cm_scrmbl_fsm_local_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 34.730s 15838.773us 199 200 99.50
sec_cm_timer_fsm_local_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 34.730s 15838.773us 199 200 99.50
otp_ctrl_sec_cm 280.240s 157320.869us 5 5 100.00
sec_cm_dai_fsm_global_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 34.730s 15838.773us 199 200 99.50
otp_ctrl_sec_cm 280.240s 157320.869us 5 5 100.00
sec_cm_lci_fsm_global_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 34.730s 15838.773us 199 200 99.50
sec_cm_kdi_fsm_global_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 34.730s 15838.773us 199 200 99.50
sec_cm_part_fsm_global_esc 205 210 97.62
otp_ctrl_parallel_lc_esc 34.730s 15838.773us 199 200 99.50
otp_ctrl_macro_errs 28.700s 4778.425us 6 10 60.00
sec_cm_scrmbl_fsm_global_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 34.730s 15838.773us 199 200 99.50
sec_cm_timer_fsm_global_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 34.730s 15838.773us 199 200 99.50
otp_ctrl_sec_cm 280.240s 157320.869us 5 5 100.00
sec_cm_part_data_reg_integrity 300 300 100.00
otp_ctrl_init_fail 7.980s 2803.648us 300 300 100.00
sec_cm_part_data_reg_bkgn_chk 33 50 66.00
otp_ctrl_check_fail 25.620s 3239.031us 33 50 66.00
sec_cm_part_mem_regren 30 30 100.00
otp_ctrl_dai_lock 43.920s 17276.646us 30 30 100.00
sec_cm_part_mem_sw_unreadable 30 30 100.00
otp_ctrl_dai_lock 43.920s 17276.646us 30 30 100.00
sec_cm_part_mem_sw_unwritable 30 30 100.00
otp_ctrl_dai_lock 43.920s 17276.646us 30 30 100.00
sec_cm_lc_part_mem_sw_noaccess 30 30 100.00
otp_ctrl_dai_lock 43.920s 17276.646us 30 30 100.00
sec_cm_access_ctrl_mubi 30 30 100.00
otp_ctrl_dai_lock 43.920s 17276.646us 30 30 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
otp_ctrl_smoke 17.740s 9819.986us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 30 30 100.00
otp_ctrl_dai_lock 43.920s 17276.646us 30 30 100.00
sec_cm_test_bus_lc_gated 10 10 100.00
otp_ctrl_smoke 17.740s 9819.986us 10 10 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 280.240s 157320.869us 5 5 100.00
sec_cm_direct_access_config_regwen 30 30 100.00
otp_ctrl_regwen 10.630s 1539.325us 30 30 100.00
sec_cm_check_trigger_config_regwen 10 10 100.00
otp_ctrl_smoke 17.740s 9819.986us 10 10 100.00
sec_cm_check_config_regwen 10 10 100.00
otp_ctrl_smoke 17.740s 9819.986us 10 10 100.00
sec_cm_macro_mem_integrity 6 10 60.00
otp_ctrl_macro_errs 28.700s 4778.425us 6 10 60.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 9.590s 3555.934us 1 1 100.00
stress_all_with_rand_reset 30 100 30.00
otp_ctrl_stress_all_with_rand_reset 601.350s 1422928.646us 30 100 30.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 35 test runs
otp_ctrl_macro_errs 53187650556272406201878765883722984222163982884003706609033716610906711418082 1890
UVM_INFO @ 224159743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 92265519573073150643160766233560436527536732437963653876234177227232771346519 5723
UVM_INFO @ 507323932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 108217073083960917785779271459429977136335070048695255392983874915223791914943 1357
UVM_INFO @ 181714905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 66184512658182975684595275939935113797986577340784638331940572414678546647548 6646
UVM_INFO @ 3170385455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 10628712028637631087393890317967224935194331562931147088767267509375693131217 3827
UVM_INFO @ 4171410430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 44290293046324406086438223226798470914911799707201885955245803999998907599929 417
UVM_INFO @ 83722965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 33000994601308948026294499253154312520794425758329244193163172766125802679287 4216
UVM_INFO @ 1004041110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 96546072756002365318181570062088072697002498379965965982742703992844342619846 3090
UVM_INFO @ 269554816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 38417764821919224155165361802826222868972970835776430433148117413876784169687 735
UVM_INFO @ 82712805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 17744289938005266853535528672817936516488494184728940331047334177580763587478 1423
UVM_INFO @ 482271303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 34009157357514203473687979492432208731042027278008155988385461739949800043896 9243
UVM_INFO @ 4541451998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 14501170120349224603186151287177571342745451146650062523477476213532565656726 1197
UVM_INFO @ 175708330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 93010979353874399167401013491925779841400225640879212770934126743502087566674 3457
UVM_INFO @ 880732951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 27068901444643492408909941632334669590324433141637139685683083054824299983623 9084
UVM_INFO @ 2590597254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 19544980926695062121404677285582830551519518170516171718577291096634909708090 8146
UVM_INFO @ 812696298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 1378648491313959598710801096220102803157570111355363243312455138841657975959 467
UVM_INFO @ 834423059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 64584535702264196418828825998721939608060414359841277639352184969958603974849 3838
UVM_INFO @ 2978679132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 40799401036467073426688298589436914809097883665458327899066542076421044443420 12034
UVM_INFO @ 1940168852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 61533961073552698033431903973489443106796119192138819729678911197966767849062 2136
UVM_INFO @ 1877352759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 34439109060478847350527982806212525755488787870936901210648510501454121385089 10584
UVM_INFO @ 5920048543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 42885879032856981988020999692140448796319422558067545409164778662567478922756 5448
UVM_INFO @ 754728125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 19729231111118271059495382212150494545713736003806157261516461413329521227128 969
UVM_INFO @ 1591780565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 47840960953719034587685809635564276406264434007475348887663077726751244627682 4848
UVM_INFO @ 647523339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 95133307428749910938544810175157696331350334787707485282900279716456310234029 4469
UVM_INFO @ 733062296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 21634149550835932695269216424050146513457272121535399090463569115330142704379 6372
UVM_INFO @ 421236529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 45401499386123127954037339610996516739026930489019240638997447236121771448855 367
UVM_INFO @ 141272154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 59600248623388696131718121269500962801309659418122570069554389920228694089110 7073
UVM_INFO @ 1977590219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 95383718482573589338460919641807515968779587811032260462483182414807249441278 2436
UVM_INFO @ 1834744148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 94306126511255241207397503938512497791358608556873961429224704404918604954608 4825
UVM_INFO @ 2051906450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 77397572065152613040733746220708343937471116531353253401383631861339863166473 240
UVM_INFO @ 5900573124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 34912749025019886804865614136617394511597875954277266900765879073471444728884 189
UVM_INFO @ 38531556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 104045211334699023875223221860748205355783218234756004522506818061177252098226 16781
UVM_INFO @ 6760571682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 45434692516521284803653789704832985313617416196142735284891789182747882623113 1655
UVM_INFO @ 171521957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 18504749073659007873191359173255547523281168034701415575476097811030862045554 153
UVM_INFO @ 161906346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 38282736318572228825899939330815213891752373489518124621562435438517512157045 5696
UVM_INFO @ 1424265418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 26 test runs
otp_ctrl_stress_all_with_rand_reset 81842983524299246962588192570820890760543616425825805368811846553466106208523 6101
UVM_INFO @ 792476056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 22861414634482998118268964551050373643254278099860172095367920852352266109969 28432
UVM_INFO @ 8366677948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 28551685057991351258418504197848095724208692104664534276596937731897426206787 14913
UVM_INFO @ 27220531835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 114658874711970848091844689249024543751637393407070322212520302863291761645402 23828
UVM_INFO @ 2747352143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 59275975549257814949452299203140535780302858863572721401654134481765680758031 18316
UVM_INFO @ 44136150303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 115700327717961497540310787191705230441848030949490302633903147370191501001793 127
UVM_INFO @ 129209246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 4970617815725521280710197127737446321597805023930471905616526336710375802714 6943
UVM_INFO @ 3861546075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 14227908196986517428645572844850925427743017462251062906877435725461191557169 5508
UVM_INFO @ 14550672472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 3926444399126020319525410843797018607886137353176161101961491472487698500771 11485
UVM_INFO @ 5439448768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 83175289779648862019315407694928413274586817517762664014507799601986100160268 10467
UVM_INFO @ 3055483155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 105743166943447750868095519170541260692155277355855726878747740022446002101105 9003
UVM_INFO @ 879700153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 39389571514691140604964310906162275284945413570632667349216620251714990581117 2409
UVM_INFO @ 612992689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 349195132737665092130529447684336919401686196510651420254444203901073954391 16391
UVM_INFO @ 2553114697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 49029875818478805416900298092699464948941342544515600087219995042135341054739 5120
UVM_INFO @ 38866585714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 1488047666451456313388153183446413493486323728867296065815768112704968496805 4255
UVM_INFO @ 1224526136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 35284762529942140573278295776551839191917351102939061275858543679874811343984 2647
UVM_INFO @ 1508497579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 68779467771538097300640008187134789482063977011790717360263697874575205314015 12551
UVM_INFO @ 2630803183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 43264721562941413870786019862901032644320510111981935469417467971442711738328 10062
UVM_INFO @ 3580909740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 33427050105867745727877165090652483511767635772716973556453601626155986782645 7802
UVM_INFO @ 2514720898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 39695114063743219598678062819400551537601576855922522669686739086683238931638 6930
UVM_INFO @ 1760109232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 17987029123987648475443897023427744735207377641835548593848023216908364759233 13583
UVM_INFO @ 11338389798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 74767192219846986409883550770554889975257272179507484420206786981340413201203 505
UVM_INFO @ 97414545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 29414838130071480322185724426941386066069891953706861612722089347122258252523 267
UVM_INFO @ 1141410527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 42260646786728007922403368699596537344670103149432055130445209779329465775058 863
UVM_INFO @ 1135648443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 93593174499789325354872811974978079226404009974354582130170831814787031209180 17838
UVM_INFO @ 31474846177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 89317254428599136331434203051045651933182235155736455094064870392343144019690 3382
UVM_INFO @ 1307542193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 18 test runs
otp_ctrl_stress_all_with_rand_reset 63553878805778458113244215425734588729554701933302740834760797984351326622122 92
UVM_INFO @ 428851599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 4163757826381974462180452228606940356767503012908303170145351216278037017035 98
UVM_INFO @ 88801823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 95084230417021186000438256105432625369279471706592692266059390580042540247932 283
UVM_INFO @ 1735169937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 39726270647006673097353710057369475202560626176143477614562297185857281053461 93
UVM_INFO @ 27692611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 80783529731981897183392130100854827895917289176521559780653769358935901647701 92
UVM_INFO @ 107671095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 15918199488460573231989274360749794047483585050262558200415613591663136826634 93
UVM_INFO @ 27908366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 67261929905367452039868250982515180025094855507913008484641537841184729238386 12558
UVM_INFO @ 6290866255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 112578042698003039749668369597001345113783682239126319909557373996131857047760 22629
UVM_INFO @ 707079043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 28792385877140718592073024268141403444511463406040343738918100628372862311555 92
UVM_INFO @ 27271548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 89072566632525379552300061803509578970118178641713023701914653629456377055364 222
UVM_INFO @ 269116349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 16307240508370460400315848105011620227276766676508323746360532247479323232831 93
UVM_INFO @ 34205189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 376123017900277829675012686720932790731439576520217355071777316610776864095 11574
UVM_INFO @ 2036682068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 692414339401590602377869834696950469071572595888613207630881664243160497935 93
UVM_INFO @ 25878086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 69820245387236507797126929037811387119293124749010227135859272197813536018398 2143
UVM_INFO @ 8677629409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 108285322502842955896480519591651601949915809320282775957063835907394643917322 2958
UVM_INFO @ 1310595093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 84508266180525240637496756532785314875279261474753282992093866650310142336846 92
UVM_INFO @ 27765499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 47393804725675058852132092629474538338600639266572052001487637254681258550644 15119
UVM_INFO @ 2984409038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 105043625669029731901943608831648969288970537808741496454712615517450994620190 302
UVM_INFO @ 84619850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 8 test runs
otp_ctrl_stress_all_with_rand_reset 110316265996053784180760185433122963661715959555602458235091937732712527795817 18522
UVM_INFO @ 7180632681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 57115718189936420346536159119189653418916351081397041342571052811715001375633 31500
UVM_INFO @ 4803825427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 80258214295906450821435377342789593903127764936429776830444078525130358824065 93
UVM_INFO @ 53714147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 60621267315296075762936958197172046391852810975012723337419667429792811352037 93
UVM_INFO @ 33487281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 72796205048750994071184553144876401620117319819207233401103785527380093728767 1980
UVM_INFO @ 484310798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 59133638764970117480213625335587264911884631509637363972821456232103148815179 92
UVM_INFO @ 71867434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 54942451930692814550036445055235585654416425104703287323187372796555352914173 93
UVM_INFO @ 27543934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 73620346454335832532628482773913389955106661978895860557226479442476183636135 142
UVM_INFO @ 5922830253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_common_vseq] wait timeout occurred! 2 test runs
otp_ctrl_csr_mem_rw_with_rand_reset 69643677915834506048896579977543151573476993599028936843434787771115182507254 96
UVM_INFO @ 10101459060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 62510698955718382705450005317995294806648804430314379137011858089186904047903 1486
UVM_INFO @ 1422928645561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(cio_test_en_o == *)' 1 test run
otp_ctrl_stress_all_with_rand_reset 44464141672243639752290087613364020898248116258649918780909138829641170346260 441
UVM_ERROR @ 13885306905 ps: (otp_ctrl_if.sv:297) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 13885306905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *d* rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 26650632946130044241095844377488521147496644831910060334375882856230350515578 94
UVM_INFO @ 5436068931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed 1 test run
otp_ctrl_stress_all_with_rand_reset 112532582422419692632956103453982702688988126415984264656062961051318857422783 1731
UVM_INFO @ 1171348473 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 1171556808 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 1174390164 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 1174640166 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 80374705426847937399259435830268776882696274675582026400346961858104726855028 7707
UVM_INFO @ 8208736526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen 1 test run
otp_ctrl_stress_all_with_rand_reset 111045962044126884255092988289361290517490177398784595781442422689927035489639 179
UVM_INFO @ 39945993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 42883173847089645623895228421737696686524926128888475551592222489492055980969 5502
UVM_INFO @ 18699292484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_check_error did not trigger max_delay:* 1 test run
otp_ctrl_parallel_lc_esc 5648241542681749622384267403435909803063768959751292862728178777128713959399 3902
UVM_INFO @ 90972710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---