| V1 |
|
100.00% |
| V2 |
|
80.54% |
| V2S |
|
100.00% |
| V3 |
|
4.00% |
| unmapped |
|
70.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 50 | 50 | 100.00 | |||
| pattgen_smoke | 5.000s | 680.442us | 50 | 50 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| pattgen_csr_hw_reset | 1.000s | 30.556us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| pattgen_csr_rw | 2.000s | 47.854us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| pattgen_csr_bit_bash | 2.000s | 332.443us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| pattgen_csr_aliasing | 1.000s | 59.620us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| pattgen_csr_mem_rw_with_rand_reset | 2.000s | 47.364us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| pattgen_csr_rw | 2.000s | 47.854us | 5 | 5 | 100.00 | |
| pattgen_csr_aliasing | 1.000s | 59.620us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| perf | 25 | 50 | 50.00 | |||
| pattgen_perf | 3601.000s | 0.000us | 25 | 50 | 50.00 | |
| cnt_rollover | 50 | 50 | 100.00 | |||
| cnt_rollover | 54.000s | 9073.703us | 50 | 50 | 100.00 | |
| error | 50 | 50 | 100.00 | |||
| pattgen_error | 2.000s | 34.802us | 50 | 50 | 100.00 | |
| stress_all | 25 | 50 | 50.00 | |||
| pattgen_stress_all | 10802.042s | 0.000us | 25 | 50 | 50.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| pattgen_alert_test | 1.000s | 60.527us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| pattgen_intr_test | 2.000s | 22.846us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| pattgen_tl_errors | 3.000s | 190.442us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| pattgen_tl_errors | 3.000s | 190.442us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| pattgen_csr_hw_reset | 1.000s | 30.556us | 1 | 1 | 100.00 | |
| pattgen_csr_rw | 2.000s | 47.854us | 5 | 5 | 100.00 | |
| pattgen_csr_aliasing | 1.000s | 59.620us | 1 | 1 | 100.00 | |
| pattgen_same_csr_outstanding | 2.000s | 114.570us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| pattgen_csr_hw_reset | 1.000s | 30.556us | 1 | 1 | 100.00 | |
| pattgen_csr_rw | 2.000s | 47.854us | 5 | 5 | 100.00 | |
| pattgen_csr_aliasing | 1.000s | 59.620us | 1 | 1 | 100.00 | |
| pattgen_same_csr_outstanding | 2.000s | 114.570us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| pattgen_tl_intg_err | 2.000s | 197.837us | 25 | 25 | 100.00 | |
| pattgen_sec_cm | 2.000s | 61.921us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| pattgen_tl_intg_err | 2.000s | 197.837us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 2 | 50 | 4.00 | |||
| pattgen_stress_all_with_rand_reset | 99.000s | 4817.158us | 2 | 50 | 4.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 35 | 50 | 70.00 | |||
| pattgen_inactive_level | 142.000s | 10005.347us | 35 | 50 | 70.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_base_vseq.sv:1287) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 47 test runs | |||
| pattgen_stress_all_with_rand_reset | 114345594687326226568270162072125223607111767573140822343039467142814234664841 | 163 |
UVM_ERROR @ 525399934 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 525399934 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 525441170 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 56133683284344795627969792672514799955489653185152695886293316657674112207132 | 255 |
UVM_ERROR @ 5252978719 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 5252978719 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 5/10
UVM_INFO @ 5253062053 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 14389769690643075888610149666769417052164497844756296668662989788597031908643 | 292 |
UVM_ERROR @ 2597845205 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2597845205 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 5/10
UVM_INFO @ 2597866039 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 88195453693757210409002977202341827816009447576562926657422841624544094724956 | 169 |
UVM_ERROR @ 415086459 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 415086459 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/5
UVM_INFO @ 415147065 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 33305642632681906245982339778078047846825968594078101710361556278130478446577 | 189 |
UVM_ERROR @ 3703624881 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3703624881 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/5
UVM_INFO @ 3703944881 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 106202167638551724631292031745597385070775563550330917695869669091524073257022 | 130 |
UVM_ERROR @ 803004481 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 803004481 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 803066983 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 36757171212698219873863381049116374609509572932464975832803775015371497138855 | 133 |
UVM_ERROR @ 5148063773 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 5148063773 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 5148357893 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 56375376685511253814850140462189131868241573655468858833059905368168573052499 | 130 |
UVM_ERROR @ 802684419 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 802684419 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 802766891 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 106716013548965332407677047011040723085713208974045184397495303267179514794223 | 252 |
UVM_ERROR @ 1613418512 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1613418512 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 1613452604 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 14503230920552303220984208649196641288961400358498666971724308335052247318207 | 149 |
UVM_ERROR @ 543517613 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 543517613 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 543569158 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 77156538780031454000104365614417105529699772764685355329638748225569624491669 | 193 |
UVM_ERROR @ 2518938883 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2518938883 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 2519061331 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 85346162339962860394167066520379378927293302540396766934725991161425191407124 | 173 |
UVM_ERROR @ 5235307479 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 5235307479 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 5235390813 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 24993041276245616051380867767887339556636244490915029820107408495135172524414 | 250 |
UVM_ERROR @ 6815567238 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 6815567238 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/10
UVM_INFO @ 6815942241 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 91686996778598960023085351609400328775338120117443548467243548304651436385384 | 123 |
UVM_ERROR @ 938235829 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 938235829 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 938298331 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 84497640715004358741045840683745300407193324956016173763926564845923879382654 | 123 |
UVM_ERROR @ 3417523293 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3417523293 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 3417731628 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 98364406567107068588238080890267646798127189915550820731115024377481164641893 | 209 |
UVM_ERROR @ 2086304571 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2086304571 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 2086384571 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 109408215185860078024227186444643968224464458002310994878718181130996626781399 | 260 |
UVM_ERROR @ 1728355788 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1728355788 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 5/10
UVM_INFO @ 1728376622 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 86001837989203112748161673175927113176232816619267909191610726369277384732479 | 175 |
UVM_ERROR @ 666757827 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 666757827 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 666838635 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 68407381414389176590447736270221641210656809718016769013529488634401246238563 | 204 |
UVM_ERROR @ 600943618 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 600943618 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 601002442 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 81471519539891593698979135907588586074122595654541033985660494815970709989414 | 118 |
UVM_ERROR @ 11358133431 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 11358133431 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 11359276287 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 3278959628256293304724280762492530151040982770164648220443733508773095857321 | 123 |
UVM_ERROR @ 3724983384 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3724983384 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 3725263384 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 25361941250286584392503133148721585419332826457909318767927155358922151593728 | 120 |
UVM_ERROR @ 8137688255 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 8137688255 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 8138243810 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 24763905067989409826458281605468242552383236292066300615658466066895548177716 | 167 |
UVM_ERROR @ 973312491 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 973312491 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 973394123 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 10541032071102460980988696535259803730713147990892098211584482193557861280721 | 117 |
UVM_ERROR @ 1571468884 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1571468884 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1571608884 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 51226997804684663973541513396289439661082108402528368115826415596255561670077 | 113 |
UVM_ERROR @ 105830348 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 105830348 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 105851182 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 84619875859102320096923180816758805559768783354081174279118907959369184600462 | 119 |
UVM_ERROR @ 2764187664 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2764187664 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 2764446923 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 33645451712246825916068972774997104195233640363027521939960389110798148843444 | 125 |
UVM_ERROR @ 976211966 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 976211966 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 976261966 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 26446470685706245589946516643159253181007268306718952737344940579821941896398 | 119 |
UVM_ERROR @ 4135031965 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4135031965 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 4135431965 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 83431957373154215995486356554693039133538096333642862360198166219889749662628 | 156 |
UVM_ERROR @ 1652957533 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1652957533 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 1653040865 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 93362743902085242162823324715077748858718482335433997552531909327158731089605 | 134 |
UVM_ERROR @ 1104232626 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1104232626 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1104580450 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 68596022261403077484984668958543025879666819510496508436037538881967006065075 | 200 |
UVM_ERROR @ 10919982628 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 10919982628 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 10920290320 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 36103754197416614200742066031257787365278573454625691800258199670173029290119 | 271 |
UVM_ERROR @ 12664553321 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 12664553321 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 12664974377 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 13369267890844731584827192171799263362958816877907243673252482139490940720217 | 134 |
UVM_ERROR @ 1668360596 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1668360596 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1668485594 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 54437366470706983447808006391010647644636392724534236606108208233617849727575 | 186 |
UVM_ERROR @ 784435921 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 784435921 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/10
UVM_INFO @ 784526830 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 52285728518695896553635132011734096594202228689872499573344762135649286924309 | 191 |
UVM_ERROR @ 4472323819 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4472323819 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 4472423818 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 33216788652661669195886427531963273969820293466725026936438893761337920292444 | 181 |
UVM_ERROR @ 1417389244 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1417389244 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 1417532100 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 60682646016912995587819759581347880244771056363242906479376123266212895704084 | 174 |
UVM_ERROR @ 655470160 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 655470160 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 655541588 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 31085977966173531032382771643751757799953923872275987307746389749542331753873 | 123 |
UVM_ERROR @ 519403883 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 519403883 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 519506973 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 75713470523982359878570043994487700713952973044849999028950969914865609658200 | 132 |
UVM_ERROR @ 934125138 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 934125138 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 934258474 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 98742976278234923971516502892438179820376851542706540012079449118080148449067 | 146 |
UVM_ERROR @ 815324726 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 815324726 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 815424726 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 39877613112797097910071525155769254463160243754093560745984365713945665577327 | 146 |
UVM_ERROR @ 845735404 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 845735404 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 845836414 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 51419183430731874343788819959342841317360423039366828566251064164018624304407 | 124 |
UVM_ERROR @ 1591017865 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1591017865 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 1591175761 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 70364066570301322019752456225113424621654670045782455917475342049084790535234 | 160 |
UVM_ERROR @ 3588183971 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3588183971 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 3588392306 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 99106542007948620814006974287331586716272353463404325404280839659669016356145 | 155 |
UVM_ERROR @ 987260347 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 987260347 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 987326137 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 11648895107486492509665040950836162881164943023183667711694510307946659067774 | 119 |
UVM_ERROR @ 806578803 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 806578803 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 806649510 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 59385452748204697374495930306575515587855866291576848253981255162159351168212 | 157 |
UVM_ERROR @ 704126719 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 704126719 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 704147127 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 55036779847034297647083613085677551100424463365078268069596134170228067818184 | 159 |
UVM_ERROR @ 966159823 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 966159823 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 966199823 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: | 22 test runs | |||
| pattgen_stress_all | 88103562459503809570823399988031019714121073641858632765250102016738160866315 | 149 |
----------------------------------------
Name Type Size Value
----------------------------------------
exp_item pattgen_item - @11180
|
|
| pattgen_stress_all | 57224526594056957056318594248036918614634862808617941628029974100824283217732 | 135 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11126
|
|
| pattgen_stress_all | 98360940156514495070363957172237678446784259278987356166675446732499816225600 | 130 |
--------------------------------------
Name Type Size Value
--------------------------------------
exp_item pattgen_item - @11079
|
|
| pattgen_stress_all | 8529070354377347524544839556652687038816604815376107011807815275685550611749 | 142 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11304
|
|
| pattgen_stress_all | 93848445718157682471395416630770044714574538634897873486409043139814005638302 | 148 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11186
|
|
| pattgen_stress_all | 106145042891191510007864292915731562631691169907919119428880449444995751881595 | 141 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11191
|
|
| pattgen_stress_all | 24300349829618994800500143860160368871653762540647091093565747847362036732837 | 125 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11104
|
|
| pattgen_stress_all | 652782472144786458215063854867579501665913373559276683652704303335709880357 | 130 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11113
|
|
| pattgen_stress_all | 112838221652757343199891643475862381791651401808813762310796184226850654033762 | 135 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @12571
|
|
| pattgen_stress_all | 42949706345258245899511583415099333796086855611471741347307968653786011429542 | 135 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11170
|
|
| pattgen_stress_all | 51776974333311170760228551720267076937496990141708774121377478620861487143776 | 148 |
-------------------------------------
Name Type Size Value
-------------------------------------
exp_item pattgen_item - @11251
|
|
| pattgen_stress_all | 84133688781122120619158490923239479650858075739387296884857340217082515160180 | 135 |
--------------------------------------
Name Type Size Value
--------------------------------------
exp_item pattgen_item - @11101
|
|
| pattgen_stress_all | 25043724669804867861828846759642646172155911005726078380119538736495581814376 | 130 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11164
|
|
| pattgen_stress_all | 88683348172913081536142906045270915793071228234366435433054855222276278144370 | 151 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11124
|
|
| pattgen_stress_all | 80167890940295006814617508563038519032490410955418320801264967079816238259091 | 153 |
-----------------------------------
Name Type Size Value
-----------------------------------
exp_item pattgen_item - @1738
|
|
| pattgen_stress_all | 61052167974463707411263043895930073174214646628929374374939358614498176960211 | 143 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11131
|
|
| pattgen_stress_all | 75429596471867914909364591541126123244689008563233280549256909520159275275815 | 137 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11142
|
|
| pattgen_stress_all | 101052320566034770034793748925026840383333233857049888749956270883613874351168 | 143 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11188
|
|
| pattgen_stress_all | 46959763285041207953212567777889449654592837751287473866338232633313035536435 | 130 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11097
|
|
| pattgen_stress_all | 41729667672618437114830324806552999395563527155524721299774960373537517652752 | 152 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11216
|
|
| pattgen_stress_all | 86367978347569171974161769794917865920781939585039790003920869461121141796499 | 140 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11134
|
|
| pattgen_stress_all | 108031978273265285972427558085410021481494139979583803093323506256102543260874 | 139 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11160
|
|
| UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | 15 test runs | |||
| pattgen_perf | 105602336332616909791489726831215146095470022582672628216784977290845342793095 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 35544610766298346904103975322216212404702798451336844863214912503644146109164 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 81471111970129901004139488727513152248593325660690502272866682349218238806098 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 84052904018050920627172905366725125257483344222028252409926463169312570644547 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 86495145520436239267845201091289219834342438205471759704629667229206422703589 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 28544877939981345391205401476489180226229315412176433042353173472384372782509 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 26034416985390693838928081352124991375352673803310290198603678137441341609467 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 20504849356781478368259305135138679174650619634477558697528835537233769997150 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 76157577950152820198038195486677872266095893845140680032502902269803822107966 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 19127368771870281116064416824803025389039032700508787124718558677224630954891 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 109661573959028983868802336937670535537397587533659465979951698057428541993702 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 16118411563950567902383182445351837183935360922815204838400432215969808693900 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 113802972284444959355824638392317464864589532341177725598522329163120075810451 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 38050901710514608162237733614148033940971811485406168941360140563349136099783 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 43593021349765530679417847003881211598028493570030442739083152901700859100338 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | 13 test runs | |||
| pattgen_perf | 105509047495054776791457061540653631979108488784352181930732475768024673711883 | None | ||
| pattgen_perf | 109428756182034740364019751684053629762612902157081256005412818235073084012469 | None | ||
| pattgen_perf | 101968394781528138680269996386558140727488307128896656671102262486157951671964 | None | ||
| pattgen_perf | 72076951353743814948764154708305282930121031198409753709710003894511811707334 | None | ||
| pattgen_stress_all | 72997888831967371817585331358014996627614353039504927150669128869333353161707 | None | ||
| pattgen_perf | 95924211971034988552093220637153415783765327461245525705424225568847751892459 | None | ||
| pattgen_perf | 40460996310971897154322053666098023250830625867754303212921752361190083491776 | None | ||
| pattgen_perf | 109897090738335910310698166549340377860498753220347233512675024242030237224738 | None | ||
| pattgen_perf | 55637317208507745010490203856578477629981467019013197271885752583211306016075 | None | ||
| pattgen_perf | 49000926615730509820612056231789605519304114344010287411483507202637095305154 | None | ||
| pattgen_stress_all | 108842582829607013251549020111801795671942133418631202648184715959781012510372 | None | ||
| pattgen_stress_all | 4483658249001917692609925165695050581292000570576773857082539220082083232325 | None | ||
| pattgen_perf | 98522739015677759867161352913997153850343695698006962342459886945602416467162 | None | ||
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) | 3 test runs | |||
| pattgen_inactive_level | 33550806056352153876099625629510086119388482975979106201936354506557882998954 | 99 |
UVM_INFO @ 10045936441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 71382190545082283874396469965025270695796317312280918667470167870493163192379 | 99 |
UVM_INFO @ 10048332019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 66492983660280665111518266069138631647429766218657939664912116931008647400501 | 99 |
UVM_INFO @ 10005346914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) | 2 test runs | |||
| pattgen_inactive_level | 98482455085065394006098675010760623790438995969735940149452368869353672160525 | 99 |
UVM_INFO @ 10099397345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 70927849311383850762354270116721287474897362788941667347204644836081928350015 | 99 |
UVM_INFO @ 10009030498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) | 2 test runs | |||
| pattgen_inactive_level | 17147304832752587648525614389087746319327193177591230316449833876953998908842 | 99 |
UVM_INFO @ 10005526256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 16788936854657731381894368009299147089312797930991774493144994409807695173121 | 99 |
UVM_INFO @ 10279550340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) | 2 test runs | |||
| pattgen_inactive_level | 62348652379296717865308878955286252874598884357372599386988042782449778731571 | 99 |
UVM_INFO @ 10004745766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 37163368168201534296399581243152714371856004857860814024561469549106828738410 | 99 |
UVM_INFO @ 10009232503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) | 2 test runs | |||
| pattgen_inactive_level | 52156723449069029916138636634214880881145236955980299486803016921380746194797 | 99 |
UVM_INFO @ 10016258852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 19034052999019865578586997026548981777622710543948743593691630471714636490958 | 99 |
UVM_INFO @ 10074830456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) | 1 test run | |||
| pattgen_inactive_level | 42875521266331365160546927598707100784221663763321247480047755525600160559872 | 99 |
UVM_INFO @ 10012961250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) | 1 test run | |||
| pattgen_inactive_level | 111060469239851615470202907386576709488531059879019043537064144322029253555917 | 99 |
UVM_INFO @ 10010925162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) | 1 test run | |||
| pattgen_inactive_level | 16588913364383754583495497911634397339219025406256780867570357973077181705726 | 99 |
UVM_INFO @ 10017398550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) | 1 test run | |||
| pattgen_inactive_level | 27779989286845683761863953616666036823130286461526389911916236748291751304130 | 99 |
UVM_INFO @ 10015380344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard] | 1 test run | |||
| pattgen_stress_all_with_rand_reset | 58353449161012616303454020967388144387945745941243252680490243690892266421236 | 138 |
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
|
|