Simulation Results: pwrmgr

 
13/06/2026 02:15:06 DVSim: v1.49.0 sha: 9424e63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.50 %
  • code
  • 97.54 %
  • assert
  • 98.96 %
  • func
  • 99.01 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 96.61 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
94.89%
V2S
100.00%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
pwrmgr_smoke 1.010s 26.433us 10 10 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 1.000s 59.469us 1 1 100.00
csr_rw 5 5 100.00
pwrmgr_csr_rw 0.990s 19.452us 5 5 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 4.630s 383.802us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.330s 26.901us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.300s 73.353us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
pwrmgr_csr_rw 0.990s 19.452us 5 5 100.00
pwrmgr_csr_aliasing 1.330s 26.901us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 10 10 100.00
pwrmgr_wakeup 1.210s 221.725us 10 10 100.00
control_clks 10 10 100.00
pwrmgr_wakeup 1.210s 221.725us 10 10 100.00
aborted_low_power 20 20 100.00
pwrmgr_aborted_low_power 1.280s 49.946us 10 10 100.00
pwrmgr_lowpower_invalid 1.030s 58.547us 10 10 100.00
reset 18 20 90.00
pwrmgr_reset 1.470s 1000.000us 8 10 80.00
pwrmgr_reset_invalid 1.260s 114.266us 10 10 100.00
main_power_glitch_reset 8 10 80.00
pwrmgr_reset 1.470s 1000.000us 8 10 80.00
reset_wakeup_race 10 10 100.00
pwrmgr_wakeup_reset 1.740s 259.197us 10 10 100.00
lowpower_wakeup_race 10 10 100.00
pwrmgr_lowpower_wakeup_race 1.420s 166.366us 10 10 100.00
disable_rom_integrity_check 9 10 90.00
pwrmgr_disable_rom_integrity_check 1.370s 153.058us 9 10 90.00
stress_all 6 10 60.00
pwrmgr_stress_all 19.660s 10750.639us 6 10 60.00
intr_test 10 10 100.00
pwrmgr_intr_test 1.020s 21.955us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
pwrmgr_tl_errors 2.910s 96.338us 25 25 100.00
tl_d_illegal_access 25 25 100.00
pwrmgr_tl_errors 2.910s 96.338us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
pwrmgr_csr_hw_reset 1.000s 59.469us 1 1 100.00
pwrmgr_csr_rw 0.990s 19.452us 5 5 100.00
pwrmgr_csr_aliasing 1.330s 26.901us 1 1 100.00
pwrmgr_same_csr_outstanding 1.150s 51.450us 5 5 100.00
tl_d_partial_access 12 12 100.00
pwrmgr_csr_hw_reset 1.000s 59.469us 1 1 100.00
pwrmgr_csr_rw 0.990s 19.452us 5 5 100.00
pwrmgr_csr_aliasing 1.330s 26.901us 1 1 100.00
pwrmgr_same_csr_outstanding 1.150s 51.450us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
pwrmgr_tl_intg_err 2.040s 197.038us 25 25 100.00
pwrmgr_sec_cm 2.900s 688.483us 5 5 100.00
prim_count_check 5 5 100.00
pwrmgr_sec_cm 2.900s 688.483us 5 5 100.00
prim_fsm_check 5 5 100.00
pwrmgr_sec_cm 2.900s 688.483us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
pwrmgr_tl_intg_err 2.040s 197.038us 25 25 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.750s 853.510us 10 10 100.00
sec_cm_rom_ctrl_intersig_mubi 20 20 100.00
pwrmgr_wakeup_reset 1.740s 259.197us 10 10 100.00
pwrmgr_repeat_wakeup_reset 3.540s 777.877us 10 10 100.00
sec_cm_rstmgr_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 1.280s 73.670us 10 10 100.00
sec_cm_esc_rx_clk_bkgn_chk 10 10 100.00
pwrmgr_esc_clk_rst_malfunc 0.970s 30.936us 10 10 100.00
sec_cm_esc_rx_clk_local_esc 5 5 100.00
pwrmgr_sec_cm 2.900s 688.483us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
pwrmgr_sec_cm 2.900s 688.483us 5 5 100.00
sec_cm_fsm_terminal 5 5 100.00
pwrmgr_sec_cm 2.900s 688.483us 5 5 100.00
sec_cm_ctrl_flow_global_esc 10 10 100.00
pwrmgr_global_esc 0.980s 32.035us 10 10 100.00
sec_cm_main_pd_rst_local_esc 10 10 100.00
pwrmgr_glitch 0.950s 113.787us 10 10 100.00
sec_cm_ctrl_config_regwen 10 10 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.820s 296.119us 10 10 100.00
sec_cm_wakeup_config_regwen 5 5 100.00
pwrmgr_csr_rw 0.990s 19.452us 5 5 100.00
sec_cm_reset_config_regwen 5 5 100.00
pwrmgr_csr_rw 0.990s 19.452us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 4 10 40.00
pwrmgr_escalation_timeout 1.180s 102.207us 4 10 40.00
stress_all_with_rand_reset 8 10 80.00
pwrmgr_stress_all_with_rand_reset 23.680s 5482.030us 8 10 80.00

Error Messages

   Test seed line log context
Offending '((!clk_en) || status)' 6 test runs
pwrmgr_escalation_timeout 97386821329430346333443747860784230868039272841208506037443331720747269242166 79
UVM_ERROR @ 102206870 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 102206870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 63583102435078837839558116571784485162961959473558670357805025444215591628068 79
UVM_ERROR @ 190323993 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 190323993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 44278922293715237168689273008156368645601495350053941871844186483757588189299 79
UVM_ERROR @ 139176190 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 139176190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 105703314266441661601119068680666651848490769604732940423537147425944272900144 79
UVM_ERROR @ 343257322 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 343257322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 94649261897509875681475767724026016110890185970405428033584918095839515495493 79
UVM_ERROR @ 331810372 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 331810372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 113764031388804978610247101630357340179434066164022348742021640080404983459417 79
UVM_ERROR @ 422746529 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 422746529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 4 test runs
pwrmgr_stress_all 31976435096019694355508520977440330779997307660807862955576907299671811542803 173
UVM_INFO @ 10457182740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 104167540196742992406168944282269866767918344704682498282786297392897520720474 320
UVM_INFO @ 10633746755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 98183654194431171759513564404145729027899526604381921803762103862250997106810 159
UVM_INFO @ 10112649680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 103793383568216357470138824644280494104736010454023204192315294931115305849109 749
UVM_INFO @ 10750639352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 3 test runs
pwrmgr_reset 91581700216873530852196840156556857002282540429989007041206788248009059403537 116
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_reset 44053565590307146325528845367644868927776264374669623916208838127071033193539 138
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 73359122334728378882366562897171341784020289524046841076520753949572631421736 88
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [pwrmgr_common_vseq] wait timeout occurred! 2 test runs
pwrmgr_stress_all_with_rand_reset 36163835278165161962122674205924103717526346309137017194571191446177547456599 1189
UVM_INFO @ 12087556908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all_with_rand_reset 71873335051478283116742307175331188734356093702871400100176462312193370232616 564
UVM_INFO @ 10780949720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---