Simulation Results: rom_ctrl/32kb

 
13/06/2026 02:15:06 DVSim: v1.49.0 sha: 9424e63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.58 %
  • code
  • 98.77 %
  • assert
  • 97.68 %
  • func
  • 99.28 %
  • line
  • 99.46 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 95.57 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.18%
V2S
96.61%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 7.620s 600.022us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 12.480s 555.442us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 6.460s 169.076us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.150s 127.834us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.670s 123.789us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.280s 174.506us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 6.460s 169.076us 5 5 100.00
rom_ctrl_csr_aliasing 5.670s 123.789us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.400s 557.166us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.220s 1087.065us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 6.370s 177.855us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 33.750s 13299.440us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 10.460s 348.214us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 6.140s 164.813us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 12.090s 184.935us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 12.090s 184.935us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 12.480s 555.442us 1 1 100.00
rom_ctrl_csr_rw 6.460s 169.076us 5 5 100.00
rom_ctrl_csr_aliasing 5.670s 123.789us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.390s 183.541us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 12.480s 555.442us 1 1 100.00
rom_ctrl_csr_rw 6.460s 169.076us 5 5 100.00
rom_ctrl_csr_aliasing 5.670s 123.789us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.390s 183.541us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 170.500s 12910.443us 18 20 90.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 25.080s 3318.732us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 296.450s 1468.033us 5 5 100.00
rom_ctrl_tl_intg_err 69.320s 400.107us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 296.450s 1468.033us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 296.450s 1468.033us 5 5 100.00
sec_cm_checker_ctr_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 170.500s 12910.443us 18 20 90.00
sec_cm_checker_ctrl_flow_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 170.500s 12910.443us 18 20 90.00
sec_cm_checker_fsm_local_esc 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 170.500s 12910.443us 18 20 90.00
sec_cm_compare_ctrl_flow_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 170.500s 12910.443us 18 20 90.00
sec_cm_compare_ctr_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 170.500s 12910.443us 18 20 90.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 296.450s 1468.033us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 296.450s 1468.033us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 7.620s 600.022us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 7.620s 600.022us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 7.620s 600.022us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 69.320s 400.107us 25 25 100.00
sec_cm_bus_local_esc 20 22 90.91
rom_ctrl_corrupt_sig_fatal_chk 170.500s 12910.443us 18 20 90.00
rom_ctrl_kmac_err_chk 10.460s 348.214us 2 2 100.00
sec_cm_mux_mubi 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 170.500s 12910.443us 18 20 90.00
sec_cm_mux_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 170.500s 12910.443us 18 20 90.00
sec_cm_ctrl_redun 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 170.500s 12910.443us 18 20 90.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 25.080s 3318.732us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 296.450s 1468.033us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 604.310s 72744.539us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 59308072374756339784859999326413976866466274487484065776625380323490220550479 79
UVM_INFO @ 177855269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 43123148559058756384528618767197749986290449932960049342641840926586466699974 79
UVM_INFO @ 86347278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 2 test runs
rom_ctrl_corrupt_sig_fatal_chk 12734557595093629231095195387443890256572291786357382673430897975465581873845 90
UVM_INFO @ 674378399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 91221331660629413704211232959221659690277649136827833615893231121192292262273 101
UVM_INFO @ 9008686069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---