Simulation Results: rom_ctrl/64kb

 
13/06/2026 02:15:06 DVSim: v1.49.0 sha: 9424e63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.72 %
  • code
  • 98.77 %
  • assert
  • 97.39 %
  • func
  • 100.00 %
  • line
  • 99.46 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 95.57 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.18%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 8.200s 935.375us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 15.050s 228.479us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 10.240s 377.429us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.740s 954.883us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 7.670s 1339.376us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 11.540s 4274.062us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 10.240s 377.429us 5 5 100.00
rom_ctrl_csr_aliasing 7.670s 1339.376us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 8.850s 1023.790us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 8.750s 727.145us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 15.470s 2104.648us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 56.090s 1119.373us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 18.790s 2196.784us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 11.660s 1029.129us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 18.380s 287.414us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 18.380s 287.414us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 15.050s 228.479us 1 1 100.00
rom_ctrl_csr_rw 10.240s 377.429us 5 5 100.00
rom_ctrl_csr_aliasing 7.670s 1339.376us 1 1 100.00
rom_ctrl_same_csr_outstanding 15.560s 303.520us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 15.050s 228.479us 1 1 100.00
rom_ctrl_csr_rw 10.240s 377.429us 5 5 100.00
rom_ctrl_csr_aliasing 7.670s 1339.376us 1 1 100.00
rom_ctrl_same_csr_outstanding 15.560s 303.520us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 279.050s 8302.357us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 63.070s 6378.881us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 590.230s 2139.125us 5 5 100.00
rom_ctrl_tl_intg_err 156.170s 1224.061us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 590.230s 2139.125us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 590.230s 2139.125us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 279.050s 8302.357us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 279.050s 8302.357us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 279.050s 8302.357us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 279.050s 8302.357us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 279.050s 8302.357us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 590.230s 2139.125us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 590.230s 2139.125us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 8.200s 935.375us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 8.200s 935.375us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 8.200s 935.375us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 156.170s 1224.061us 25 25 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 279.050s 8302.357us 20 20 100.00
rom_ctrl_kmac_err_chk 18.790s 2196.784us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 279.050s 8302.357us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 279.050s 8302.357us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 279.050s 8302.357us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 63.070s 6378.881us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 590.230s 2139.125us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 386.820s 10504.877us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 55628376085950278263789606547600567128979669348702086693929130347478131338468 79
UVM_INFO @ 248046829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 104854976686401041621806818318364832702647133235877807051393983470492013440759 79
UVM_INFO @ 2104648455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---