| V1 |
|
100.00% |
| V2 |
|
85.83% |
| V2S |
|
100.00% |
| V3 |
|
40.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 2.620s | 1636.086us | 20 | 20 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.820s | 21.295us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| rv_timer_csr_rw | 0.910s | 17.868us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_timer_csr_bit_bash | 3.790s | 2126.097us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rv_timer_csr_aliasing | 1.070s | 29.453us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.460s | 122.311us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| rv_timer_csr_rw | 0.910s | 17.868us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.070s | 29.453us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 2 | 20 | 10.00 | |||
| rv_timer_random_reset | 4.550s | 1195.709us | 2 | 20 | 10.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 3.410s | 3289.573us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 535.740s | 541223.789us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 535.740s | 541223.789us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 10.440s | 6496.446us | 20 | 20 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| rv_timer_alert_test | 0.850s | 17.654us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| rv_timer_intr_test | 0.870s | 13.689us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| rv_timer_tl_errors | 3.470s | 61.828us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| rv_timer_tl_errors | 3.470s | 61.828us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.820s | 21.295us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.910s | 17.868us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.070s | 29.453us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.980s | 144.757us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.820s | 21.295us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.910s | 17.868us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.070s | 29.453us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.980s | 144.757us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| rv_timer_sec_cm | 1.190s | 850.959us | 5 | 5 | 100.00 | |
| rv_timer_tl_intg_err | 1.790s | 245.127us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| rv_timer_tl_intg_err | 1.790s | 245.127us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 4 | 10 | 40.00 | |||
| rv_timer_min | 0.930s | 219.269us | 4 | 10 | 40.00 | |
| max_value | 0 | 10 | 0.00 | |||
| rv_timer_max | 0.940s | 476.772us | 0 | 10 | 0.00 | |
| stress_all_with_rand_reset | 12 | 20 | 60.00 | |||
| rv_timer_stress_all_with_rand_reset | 57.930s | 6510.951us | 12 | 20 | 60.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | 24 test runs | |||
| rv_timer_random_reset | 99206669119886592225251869151526585506608402854242282662945355884447898376152 | 75 |
UVM_INFO @ 777707030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 48820865427465725262781469931250733244936481815282330881282905863239135515501 | 75 |
UVM_INFO @ 66906057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 59504008726574319723614585825831096504511592595699300812583193862558101307877 | 76 |
UVM_INFO @ 137849048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 51596243242229208562919285354430779536313300923910181968746445328158951601484 | 76 |
UVM_INFO @ 219269211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 3139188091095867800370619719176811658591526523894901300131401826268787601191 | 76 |
UVM_INFO @ 787876020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 18580460839571371601658293018680964149155014386381666802349356059931519106173 | 75 |
UVM_INFO @ 331286146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 19518870896898440038123699117774505536205733268156431506327979843694156049258 | 76 |
UVM_INFO @ 116110707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 36608215164827448225250253125168931606641881253951163920035262868005407880160 | 76 |
UVM_INFO @ 7822863807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 27590950612580794094367902361334035868982041785048691320630151861158051336155 | 78 |
UVM_INFO @ 126997156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 31362254260503559933387286728409366903736491478234672825323735442483759016584 | 75 |
UVM_INFO @ 105628738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 15444010435661658152519157961454628270769357371604230397101832199644908887902 | 76 |
UVM_INFO @ 79395380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 67263326248278794775784102180502511258787014820600315088655770789456046338625 | 75 |
UVM_INFO @ 70518063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 106111908663770278092611877913014033015333648767376512502332634743987492941410 | 75 |
UVM_INFO @ 77692101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 101234262979240261347904887215328768358461330850023533041847935645334277700579 | 75 |
UVM_INFO @ 84389842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 82992891006317222278117626472322148029110142621953162649385440533205934847197 | 75 |
UVM_INFO @ 63702142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 67161932908993962562809597872166530447459087016533514837333336161733125181080 | 75 |
UVM_INFO @ 1413023689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 113239929753052027429012948409807614190193194126107360871727413401256783882240 | 75 |
UVM_INFO @ 263976967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 92815283951466583176788710057458925949044466993410622171774237578881534964144 | 76 |
UVM_INFO @ 1195708918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 84304546408048751659506176551408957120415477251557156481195741450289631354318 | 75 |
UVM_INFO @ 569078590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 50800170058261288587377488042698467366826934598672326513133057339245804313575 | 75 |
UVM_INFO @ 1446068322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 49862796741455435313997406432717620050112310371577648962133916714493969183410 | 77 |
UVM_INFO @ 876050680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 96721959159759532268525008358993379033891044312937216275131434879240020364891 | 75 |
UVM_INFO @ 611411347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 6719695350877149328372084057773784908784381872385473041345860464189203705480 | 75 |
UVM_INFO @ 398737522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 6945306095731136066310883655182074901826620877777938444245100469322334196384 | 77 |
UVM_INFO @ 631084197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 10 test runs | |||
| rv_timer_max | 30627814466906570790251160848223498116869567570080472439111961106152865216549 | 76 |
UVM_INFO @ 168854326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 92823189920844663928742572443686624594578913385210336500935437051156511178323 | 75 |
UVM_INFO @ 45836908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 23064489781925266852547313576011864150961321015043983477698410812574485647202 | 75 |
UVM_INFO @ 45173122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 107831174511162186254488767984969970426210153287588559015905624798368341659287 | 76 |
UVM_INFO @ 87986179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 94275962207403715567439841515044742263264601359797078691831792086257106043262 | 75 |
UVM_INFO @ 179897437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 39096277495237929528335110087410676277178498358316284487159990954867170037211 | 75 |
UVM_INFO @ 92701794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 4393139334805788576880906032176824023155528394256031055611305997126615324023 | 75 |
UVM_INFO @ 51036959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 11144717222892701067212853830233465758667145756002726110799754071946948070827 | 75 |
UVM_INFO @ 476772178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 107045314711442381172639057059481597957965974457425233869543698569958638286632 | 75 |
UVM_INFO @ 82324569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 112279109229300887964489554970261855082399611420601322768518733955529934851601 | 75 |
UVM_INFO @ 50460145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | 4 test runs | |||
| rv_timer_stress_all_with_rand_reset | 34845051852773874584907668076677528917387793880410743080588319625023921623795 | 249 |
UVM_INFO @ 13949159521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 149252809848324653098761634221713281908974750673990708782747018334630982397 | 79 |
UVM_INFO @ 12675783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 82934428927461643544628088335210115636646970714401216640495444236235733099616 | 157 |
UVM_INFO @ 2878120973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 93783148531626487903125451438082766415923895120088631589238447514891024744866 | 110 |
UVM_INFO @ 21336359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) | 4 test runs | |||
| rv_timer_stress_all_with_rand_reset | 106844350971697491845808428993520573667363937510397103728344443354584415570182 | 80 |
UVM_INFO @ 70643648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 49564477518165677720160675831001317927976831620683639249514887085434329143614 | 81 |
UVM_INFO @ 314343366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 42514892878803599181374178586680418868131676601517839688331613026637670247876 | 137 |
UVM_INFO @ 1061405285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 3901513091544923397346676305347228390201844728865883661931767128567225076869 | 147 |
UVM_INFO @ 7824530596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|