Simulation Results: spi_host

 
13/06/2026 02:15:06 DVSim: v1.49.0 sha: 9424e63 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.13 %
  • code
  • 95.03 %
  • assert
  • 96.60 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.45%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 31.000s 3326.949us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 31.582us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 1.000s 49.322us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 144.556us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 31.181us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 32.525us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 1.000s 49.322us 5 5 100.00
spi_host_csr_aliasing 2.000s 31.181us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 2.000s 38.910us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 20.751us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 25.358us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 24.000s 2902.734us 10 10 100.00
spi_host_error_cmd 2.000s 20.308us 10 10 100.00
spi_host_event 256.000s 23352.106us 10 10 100.00
clock_rate 10 10 100.00
spi_host_speed 6.000s 964.305us 10 10 100.00
speed 10 10 100.00
spi_host_speed 6.000s 964.305us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 6.000s 964.305us 10 10 100.00
upper_range_clkdiv 4 5 80.00
spi_host_upper_range_clkdiv 369.000s 200000.000us 4 5 80.00
sw_reset 10 10 100.00
spi_host_sw_reset 11.000s 572.828us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 38.888us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 6.000s 964.305us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 6.000s 964.305us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 31.000s 3326.949us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 31.000s 3326.949us 10 10 100.00
stress_all 10 10 100.00
spi_host_stress_all 55.000s 3067.684us 10 10 100.00
spien 10 10 100.00
spi_host_spien 16.000s 1104.029us 10 10 100.00
stall 10 10 100.00
spi_host_status_stall 453.000s 476842.968us 10 10 100.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 13.000s 6761.411us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 24.000s 2902.734us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 2.000s 37.863us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 42.390us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 3.000s 329.723us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 3.000s 329.723us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 31.582us 1 1 100.00
spi_host_csr_rw 1.000s 49.322us 5 5 100.00
spi_host_csr_aliasing 2.000s 31.181us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 21.605us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 31.582us 1 1 100.00
spi_host_csr_rw 1.000s 49.322us 5 5 100.00
spi_host_csr_aliasing 2.000s 31.181us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 21.605us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 2.000s 105.073us 25 25 100.00
spi_host_sec_cm 2.000s 124.262us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 2.000s 105.073us 25 25 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
spi_host_upper_range_clkdiv 109696095237838037947316876220244532416093654562374481065663699363688331093326 115
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---