Simulation Results: sram_ctrl/main

 
13/06/2026 02:15:06 DVSim: v1.49.0 sha: 9424e63 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.20 %
  • code
  • 96.91 %
  • assert
  • 98.10 %
  • func
  • 96.60 %
  • block
  • 96.30 %
  • line
  • 97.05 %
  • branch
  • 94.50 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
84.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 7.000s 690.722us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 23.827us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 13.256us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 372.317us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 27.831us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 1408.696us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 13.256us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 27.831us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 291.000s 69642.430us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 144.000s 67350.637us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 63.000s 40376.600us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 216.000s 14101.656us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 226.000s 60547.481us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 118.000s 84331.628us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 73.000s 54667.760us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 49.000s 8250.483us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 8.000s 2752.914us 8 8 100.00
sram_ctrl_partial_access_b2b 394.000s 26725.967us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 9.000s 7329.836us 0 8 0.00
sram_ctrl_throughput_w_partial_write 7.000s 1451.733us 0 8 0.00
sram_ctrl_throughput_w_readback 7.000s 5109.785us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 30.000s 3188.945us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 4.000s 704.391us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 636.000s 69881.580us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 17.228us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 153.398us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 153.398us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 23.827us 1 1 100.00
sram_ctrl_csr_rw 2.000s 13.256us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 27.831us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 20.850us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 23.827us 1 1 100.00
sram_ctrl_csr_rw 2.000s 13.256us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 27.831us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 20.850us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 47.000s 14112.494us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 5.000s 570.774us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 1408.735us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 570.774us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 4.000s 1408.735us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 30.000s 3188.945us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 30.000s 3188.945us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 13.256us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 49.000s 8250.483us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 49.000s 8250.483us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 49.000s 8250.483us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 73.000s 54667.760us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 7.000s 1341.410us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 47.000s 14112.494us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 7.000s 1339.865us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 7.000s 690.722us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 7.000s 690.722us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 49.000s 8250.483us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 570.774us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 73.000s 54667.760us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 570.774us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 570.774us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 7.000s 690.722us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 570.774us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 8 100.00
sram_ctrl_stress_all_with_rand_reset 46.000s 1637.613us 8 8 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 114229320641542513202299254302272420582661918847707995896810074877624008806092 86
UVM_INFO @ 1319226849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 28315652815118922249011011075349985692930176477515081099265085173837695268063 86
UVM_INFO @ 663997238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 58586597328293710064087860319409852221403052633285667401025853131336198655012 86
UVM_INFO @ 1347219421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 5404930322318357464922145684814063908453651420576958366402351390499080630841 86
UVM_INFO @ 662730230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 89100122666875282464019926989858118858113501536212207609492706426965946684287 86
UVM_INFO @ 673945229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 111724219856870762437343914820865100860827905359863783613125042007037838627447 86
UVM_INFO @ 1402440767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 67770177236893303288201830343890014096166974547353670089099819151450042863676 86
UVM_INFO @ 2639062050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 585952216572603314862793489994108763215499316034283968812217540217700831228 86
UVM_INFO @ 4104575867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 55584855688547980668892582494377595358120333636662908255265400112465013456741 86
UVM_INFO @ 2748302713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 2694481372270040117338508625681492771747624949334909897352324057550188551013 86
UVM_INFO @ 2629251620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 35256082081688122369392750061790030171239786594355771844997720505230088004948 86
UVM_INFO @ 668566532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 105674648617903001325780323301765298621937801377949050781100309324920112695060 86
UVM_INFO @ 698165877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 92009604792808141445265531284331690922217968801261604699972573741908446040906 86
UVM_INFO @ 666878127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 104479174443714085717415994148584649162217822687227044053185285058000772852154 86
UVM_INFO @ 3680716509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 84346074158679187098975943103162196143349085172829576515339236931296721403779 86
UVM_INFO @ 7329836429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 88267476711899127755653788333214957368738500595375858019540832763771398147166 86
UVM_INFO @ 1451732536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 99068861888154496888097330119827562435737272899303029084651960977850407353268 86
UVM_INFO @ 5109784615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 96459653600907840204424222393388718903076737502078993774900487847671829282194 86
UVM_INFO @ 710673365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 106131166899735248000935747937881648075765142966293121828794168612402972809256 86
UVM_INFO @ 686030333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 62444663634028404161350107692973871508296923141677577358368789212842021814086 86
UVM_INFO @ 1952216953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 3164013074016462976958387303382359504635188440922078015560300924276552132638 86
UVM_INFO @ 695393393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 98845372672557493602911936586365218727061020154412736635376619647773736553517 86
UVM_INFO @ 1387076041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 113645946530848449354879900313207792606594488002514857715845270442020504097657 86
UVM_INFO @ 738281804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 26420176770787367571178861241513140854046695500624861496833205651490241588294 86
UVM_INFO @ 713948045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---