Simulation Results: sysrst_ctrl

 
13/06/2026 02:15:06 DVSim: v1.49.0 sha: 9424e63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.93 %
  • code
  • 98.41 %
  • assert
  • 98.75 %
  • func
  • 90.64 %
  • line
  • 99.42 %
  • branch
  • 99.52 %
  • cond
  • 97.60 %
  • toggle
  • 100.00 %
  • FSM
  • 95.51 %
Validation stages
V1
100.00%
V2
97.90%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
sysrst_ctrl_smoke 5.350s 2110.454us 10 10 100.00
input_output_inverted 10 10 100.00
sysrst_ctrl_in_out_inverted 9.070s 2439.815us 10 10 100.00
combo_detect_ec_rst 5 5 100.00
sysrst_ctrl_combo_detect_ec_rst 8.650s 2405.054us 5 5 100.00
combo_detect_ec_rst_with_pre_cond 5 5 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 7.380s 2292.611us 5 5 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 12.110s 4016.481us 1 1 100.00
csr_rw 5 5 100.00
sysrst_ctrl_csr_rw 6.570s 2031.635us 5 5 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 35.120s 57131.009us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 11.660s 3156.693us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 5.780s 2039.861us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sysrst_ctrl_csr_rw 6.570s 2031.635us 5 5 100.00
sysrst_ctrl_csr_aliasing 11.660s 3156.693us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 25 25 100.00
sysrst_ctrl_combo_detect 411.790s 183124.335us 25 25 100.00
combo_detect_with_pre_cond 94 100 94.00
sysrst_ctrl_combo_detect_with_pre_cond 448.520s 232964.083us 94 100 94.00
auto_block_key_outputs 25 25 100.00
sysrst_ctrl_auto_blk_key_output 33.510s 194189.039us 25 25 100.00
keyboard_input_triggered_interrupt 50 50 100.00
sysrst_ctrl_edge_detect 806.620s 435810.966us 50 50 100.00
pin_output_keyboard_inversion_control 10 10 100.00
sysrst_ctrl_pin_override_test 8.550s 2510.315us 10 10 100.00
pin_input_value_accessibility 10 10 100.00
sysrst_ctrl_pin_access_test 6.450s 2029.764us 10 10 100.00
ec_power_on_reset 10 10 100.00
sysrst_ctrl_ec_pwr_on_rst 647.110s 1175388.316us 10 10 100.00
flash_write_protect_output 10 10 100.00
sysrst_ctrl_flash_wr_prot_out 8.890s 2610.676us 10 10 100.00
ultra_low_power_test 24 25 96.00
sysrst_ctrl_ultra_low_pwr 44.620s 1661871.072us 24 25 96.00
sysrst_ctrl_feature_disable 2 2 100.00
sysrst_ctrl_feature_disable 71.320s 33559.785us 2 2 100.00
stress_all 10 10 100.00
sysrst_ctrl_stress_all 731.100s 1134612.924us 10 10 100.00
alert_test 10 10 100.00
sysrst_ctrl_alert_test 6.680s 2011.447us 10 10 100.00
intr_test 10 10 100.00
sysrst_ctrl_intr_test 7.200s 2010.152us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sysrst_ctrl_tl_errors 9.290s 2048.889us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sysrst_ctrl_tl_errors 9.290s 2048.889us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sysrst_ctrl_csr_hw_reset 12.110s 4016.481us 1 1 100.00
sysrst_ctrl_csr_rw 6.570s 2031.635us 5 5 100.00
sysrst_ctrl_csr_aliasing 11.660s 3156.693us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 21.930s 7452.785us 5 5 100.00
tl_d_partial_access 12 12 100.00
sysrst_ctrl_csr_hw_reset 12.110s 4016.481us 1 1 100.00
sysrst_ctrl_csr_rw 6.570s 2031.635us 5 5 100.00
sysrst_ctrl_csr_aliasing 11.660s 3156.693us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 21.930s 7452.785us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
sysrst_ctrl_sec_cm 70.410s 42010.371us 5 5 100.00
sysrst_ctrl_tl_intg_err 87.610s 42473.682us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
sysrst_ctrl_tl_intg_err 87.610s 42473.682us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 9 10 90.00
sysrst_ctrl_stress_all_with_rand_reset 15.680s 7532.952us 9 10 90.00

Error Messages

   Test seed line log context
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(3) +/-* 2 test runs
sysrst_ctrl_combo_detect_with_pre_cond 114354869448691735865857946767423417225730139552216808394995830101060938061552 663
UVM_ERROR @ 27586331199 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(8) vs exp(3) +/-4
UVM_INFO @ 27586331199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_combo_detect_with_pre_cond 60345272253307357676290956557869594568345132392396726208481414951133292182968 667
UVM_ERROR @ 13753103783 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(8) vs exp(3) +/-4
UVM_INFO @ 13753103783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_flash_wr_prot_vseq.sv:55) [sysrst_ctrl_flash_wr_prot_vseq] Check failed cfg.vif.flash_wp_l == * (* [*] vs * [*]) 1 test run
sysrst_ctrl_stress_all_with_rand_reset 113829744467441534252338440876106734465652340314023478372751807281070389068511 727
UVM_INFO @ 11817498580 ps: (cip_base_vseq.sv:1223) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
Stress w/ reset is done for run 10/10
UVM_INFO @ 11854531059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)  1 test run
sysrst_ctrl_ultra_low_pwr 87546735288960308594851035124536995060371908241880243538955493213872633833080 657
UVM_INFO @ 4907795508 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_INFO @ 6857795508 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 6876212480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(2) +/-* 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 108586641669226616591709514851812939840702749650257714081736127183513063162894 694
UVM_INFO @ 68144267315 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x1a
UVM_INFO @ 68144298566 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x10
UVM_INFO @ 68373613644 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0
UVM_INFO @ 68373670489 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(9) vs exp(4) +/-* 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 97957407703836304644775346391039297374022962431372029602623561881733660182422 667
UVM_ERROR @ 14809231426 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(9) vs exp(4) +/-4
UVM_INFO @ 14809231426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 36182954277442317001286681221927250105867397576314369549815869206002461058571 717
UVM_ERROR @ 86425792809 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 86425792809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-* 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 90934215511327339206754887420476594163016547771917079239022791843415020983576 667
UVM_ERROR @ 14283936698 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(2) +/-4
UVM_INFO @ 14283936698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---