Simulation Results: uart

 
13/06/2026 02:15:06 DVSim: v1.49.0 sha: 9424e63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.29 %
  • code
  • 96.86 %
  • assert
  • 98.85 %
  • func
  • 99.16 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 98.25 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
97.48%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
uart_smoke 13.580s 6254.634us 10 10 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.920s 69.895us 1 1 100.00
csr_rw 5 5 100.00
uart_csr_rw 0.920s 11.534us 5 5 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.560s 161.768us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.010s 37.294us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
uart_csr_mem_rw_with_rand_reset 1.120s 164.393us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
uart_csr_rw 0.920s 11.534us 5 5 100.00
uart_csr_aliasing 1.010s 37.294us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 10 10 100.00
uart_tx_rx 223.530s 121687.973us 10 10 100.00
parity 20 20 100.00
uart_smoke 13.580s 6254.634us 10 10 100.00
uart_tx_rx 223.530s 121687.973us 10 10 100.00
parity_error 20 20 100.00
uart_intr 235.440s 209185.260us 10 10 100.00
uart_rx_parity_err 88.890s 134646.513us 10 10 100.00
watermark 20 20 100.00
uart_tx_rx 223.530s 121687.973us 10 10 100.00
uart_intr 235.440s 209185.260us 10 10 100.00
fifo_full 10 10 100.00
uart_fifo_full 166.450s 129626.902us 10 10 100.00
fifo_overflow 10 10 100.00
uart_fifo_overflow 260.320s 201902.326us 10 10 100.00
fifo_reset 200 200 100.00
uart_fifo_reset 300.320s 139431.903us 200 200 100.00
rx_frame_err 10 10 100.00
uart_intr 235.440s 209185.260us 10 10 100.00
rx_break_err 10 10 100.00
uart_intr 235.440s 209185.260us 10 10 100.00
rx_timeout 10 10 100.00
uart_intr 235.440s 209185.260us 10 10 100.00
perf 10 10 100.00
uart_perf 621.760s 24795.311us 10 10 100.00
sys_loopback 10 10 100.00
uart_loopback 23.880s 12275.599us 10 10 100.00
line_loopback 10 10 100.00
uart_loopback 23.880s 12275.599us 10 10 100.00
rx_noise_filter 2 10 20.00
uart_noise_filter 15.840s 71264.496us 2 10 20.00
rx_start_bit_filter 10 10 100.00
uart_rx_start_bit_filter 48.950s 43668.228us 10 10 100.00
tx_overide 10 10 100.00
uart_tx_ovrd 18.270s 6554.227us 10 10 100.00
rx_oversample 10 10 100.00
uart_rx_oversample 44.090s 7486.431us 10 10 100.00
long_b2b_transfer 10 10 100.00
uart_long_xfer_wo_dly 769.050s 156712.141us 10 10 100.00
stress_all 8 10 80.00
uart_stress_all 350.730s 312148.445us 8 10 80.00
alert_test 10 10 100.00
uart_alert_test 0.910s 36.693us 10 10 100.00
intr_test 10 10 100.00
uart_intr_test 0.940s 14.252us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
uart_tl_errors 2.540s 126.941us 25 25 100.00
tl_d_illegal_access 25 25 100.00
uart_tl_errors 2.540s 126.941us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
uart_csr_hw_reset 0.920s 69.895us 1 1 100.00
uart_csr_rw 0.920s 11.534us 5 5 100.00
uart_csr_aliasing 1.010s 37.294us 1 1 100.00
uart_same_csr_outstanding 1.120s 133.680us 5 5 100.00
tl_d_partial_access 12 12 100.00
uart_csr_hw_reset 0.920s 69.895us 1 1 100.00
uart_csr_rw 0.920s 11.534us 5 5 100.00
uart_csr_aliasing 1.010s 37.294us 1 1 100.00
uart_same_csr_outstanding 1.120s 133.680us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
uart_sec_cm 1.250s 145.849us 5 5 100.00
uart_tl_intg_err 1.750s 338.858us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
uart_tl_intg_err 1.750s 338.858us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 18 20 90.00
uart_stress_all_with_rand_reset 77.110s 9751.713us 18 20 90.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 5 test runs
uart_noise_filter 4447266827195346757798686690692698049269565006657346659553558412758174676789 74
UVM_ERROR @ 11399298 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 12096267 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 12672024 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 13237680 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 24295537104845893449964810777632941501170857254239596033766043248056788208567 74
UVM_ERROR @ 94228984 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 94228984 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 142272188 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 142272188 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 20854192456731142450149059369213851792731136706147634160586677771661534202610 76
UVM_ERROR @ 15908063134 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 15908134562 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 15908313132 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (144 [0x90] vs 223 [0xdf]) reg name: uart_reg_block.rdata
UVM_ERROR @ 16334702578 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
uart_noise_filter 84286892256449881182963277396838905993566775805664980577713000322951412850716 74
UVM_ERROR @ 27517741 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 29434400 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 41601018 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 43101012 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all_with_rand_reset 19642315458193160714655947785963898318839598895380710382417467035723506960151 157
UVM_ERROR @ 2094381273 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_INFO @ 2109411765 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/942
UVM_INFO @ 2198125341 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/942
UVM_INFO @ 2262430949 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/942
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 3 test runs
uart_noise_filter 84523334422771417581925483747844505607360566979041708357341240730884911253264 74
UVM_ERROR @ 874106915 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 874398584 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 151 [0x97]) reg name: uart_reg_block.rdata
UVM_ERROR @ 1092483662 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 1092566996 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
uart_stress_all 71150496247584514491360915029786545338100793473581457808231457672793191325092 157
UVM_ERROR @ 107157211110 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 107157249572 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (96 [0x60] vs 254 [0xfe]) reg name: uart_reg_block.rdata
UVM_ERROR @ 108326725144 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 108326725144 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 31518770209215663826517282126722035340207616830771581063205583798138539414495 78
UVM_ERROR @ 48405342730 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 48405734032 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (233 [0xe9] vs 254 [0xfe]) reg name: uart_reg_block.rdata
UVM_ERROR @ 48839687950 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4, clk_pulses: 0
UVM_ERROR @ 48839774906 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 2 test runs
uart_noise_filter 95429657866164881218639258868845559715703060130557467720883981297194111877276 77
UVM_ERROR @ 28038617223 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 28038617223 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 28801717223 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 28801717223 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
uart_stress_all 37285989835495106320389710036065029930091400207390332152207115510860046077530 116
UVM_ERROR @ 38221868330 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 38221868330 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 38277968330 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 6, clk_pulses: 0
UVM_ERROR @ 38278068330 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (185 [0xb9] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR (cip_base_vseq.sv:1286) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
uart_stress_all_with_rand_reset 85486780186420488179394826751633961454661119764116020821006473635504493964030 109
UVM_ERROR @ 708255372 ps: (cip_base_vseq.sv:1199) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 708255372 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Issuing reset for run 3/5
UVM_INFO @ 708259788 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2
UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr 1 test run
uart_noise_filter 3959795846401395671227112642312677815101927931660059611204977308216335064165 79
UVM_ERROR @ 5686939171 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 5708252281 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 5708252281 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 5824939033 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1