Simulation Results: adc_ctrl

 
20/06/2026 02:47:04 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 67.56 %
  • code
  • 96.19 %
  • assert
  • 92.71 %
  • func
  • 13.79 %
  • line
  • 98.89 %
  • branch
  • 97.46 %
  • cond
  • 87.55 %
  • toggle
  • 99.76 %
  • FSM
  • 97.30 %
Validation stages
V1
100.00%
V2
50.85%
V2S
100.00%
V3
20.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
adc_ctrl_smoke 16.840s 5928.508us 10 10 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 3.350s 1220.116us 1 1 100.00
csr_rw 5 5 100.00
adc_ctrl_csr_rw 2.040s 370.283us 5 5 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 69.380s 26721.396us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.950s 883.806us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 2.870s 601.738us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
adc_ctrl_csr_rw 2.040s 370.283us 5 5 100.00
adc_ctrl_csr_aliasing 2.950s 883.806us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 10 0.00
adc_ctrl_filters_polled 2.020s 514.730us 0 10 0.00
filters_polled_fixed 0 10 0.00
adc_ctrl_filters_polled_fixed 1.990s 502.244us 0 10 0.00
filters_interrupt 0 10 0.00
adc_ctrl_filters_interrupt 2.090s 478.959us 0 10 0.00
filters_interrupt_fixed 0 10 0.00
adc_ctrl_filters_interrupt_fixed 1.970s 447.192us 0 10 0.00
filters_wakeup 0 10 0.00
adc_ctrl_filters_wakeup 2.010s 492.555us 0 10 0.00
filters_wakeup_fixed 0 10 0.00
adc_ctrl_filters_wakeup_fixed 2.040s 492.163us 0 10 0.00
filters_both 0 10 0.00
adc_ctrl_filters_both 2.310s 515.881us 0 10 0.00
clock_gating 0 10 0.00
adc_ctrl_clock_gating 1.880s 478.991us 0 10 0.00
poweron_counter 10 10 100.00
adc_ctrl_poweron_counter 8.310s 3749.370us 10 10 100.00
lowpower_counter 10 10 100.00
adc_ctrl_lowpower_counter 93.320s 46087.186us 10 10 100.00
fsm_reset 10 10 100.00
adc_ctrl_fsm_reset 266.530s 132473.555us 10 10 100.00
stress_all 3 10 30.00
adc_ctrl_stress_all 282.040s 182200.789us 3 10 30.00
alert_test 10 10 100.00
adc_ctrl_alert_test 2.090s 450.091us 10 10 100.00
intr_test 10 10 100.00
adc_ctrl_intr_test 1.920s 460.066us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
adc_ctrl_tl_errors 3.710s 568.039us 25 25 100.00
tl_d_illegal_access 25 25 100.00
adc_ctrl_tl_errors 3.710s 568.039us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
adc_ctrl_csr_hw_reset 3.350s 1220.116us 1 1 100.00
adc_ctrl_csr_rw 2.040s 370.283us 5 5 100.00
adc_ctrl_csr_aliasing 2.950s 883.806us 1 1 100.00
adc_ctrl_same_csr_outstanding 6.840s 4525.927us 5 5 100.00
tl_d_partial_access 12 12 100.00
adc_ctrl_csr_hw_reset 3.350s 1220.116us 1 1 100.00
adc_ctrl_csr_rw 2.040s 370.283us 5 5 100.00
adc_ctrl_csr_aliasing 2.950s 883.806us 1 1 100.00
adc_ctrl_same_csr_outstanding 6.840s 4525.927us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
adc_ctrl_sec_cm 12.410s 8139.463us 5 5 100.00
adc_ctrl_tl_intg_err 24.490s 8322.975us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
adc_ctrl_tl_intg_err 24.490s 8322.975us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 10 20.00
adc_ctrl_stress_all_with_rand_reset 10.290s 2119.328us 2 10 20.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 95 test runs
adc_ctrl_filters_polled 5325272742997101677009037265518823922138096177834711978535940906407123053830 386
UVM_INFO @ 502632644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 93731892843816359921362016814893637607289190094319314249104253956061512834863 386
UVM_INFO @ 371325125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 76539788567337919452227534106831446228425687177625325776648349388852624995622 386
UVM_INFO @ 369357932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 23384765077816057183736929362309865348377554860132265203720186772510483765064 386
UVM_INFO @ 413652960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 63002213928906586126546459721864088367235047542710979286763939013789172025665 386
UVM_INFO @ 328077225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 57791680826561301065778528886346440191401122448355569154488796078152085668819 386
UVM_INFO @ 306560767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 34595971813732663103725661811983127316704066622332978895792227504380827515904 386
UVM_INFO @ 354331853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 35924397592212004910472733999251733379617337103394214187036837827883619483318 386
UVM_INFO @ 515881140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 108070010137828683754872502897322076346996054966032421180107684813951615301050 399
UVM_INFO @ 742919600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 77382765487863628817709304522714834304780674362812410189494749436367659867026 386
UVM_INFO @ 541504686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 90186118121065632772812593271438107137133344132610731025172678027701343315531 386
UVM_INFO @ 343878952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 31052998481571187502674487866865991353031815854551194279332275914906229048998 386
UVM_INFO @ 455513167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 40402792757631139898049258622226056953296679298867324180957747242141894843044 386
UVM_INFO @ 326784376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 45564139041976381028760843681081225859997174720768555175947522936375746000920 386
UVM_INFO @ 509671000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 34734148970787902964455502770166948019308476239564926000025193678622941757172 386
UVM_INFO @ 315487817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 42391388467028423957830124188598189195130532516060175199230206486015389377333 386
UVM_INFO @ 329843765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 104360421591174754357129144615610524001002106468399197130082728691086621362789 386
UVM_INFO @ 386282157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 90996174397482220621669940520804907996347724431356306716274466058237463052142 392
UVM_INFO @ 573988312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 104339833206407141133735620285265294127637993103464638439908401279352179267264 386
UVM_INFO @ 407029698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 34545202617536531678078232309775284815256250552575731121260956303344317806936 386
UVM_INFO @ 416541478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 19480130353512390497938405236109531677632497287381352420168504880000127174112 386
UVM_INFO @ 285265128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 54352376615951793710885500481172241240610219794955241347040185717886470325242 386
UVM_INFO @ 378907093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 28549554786661274335766502084684419600701346092605063801364395140671369978300 386
UVM_INFO @ 473382540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 115586030394322133652133598749032239610678891503691392989432808797708962820391 386
UVM_INFO @ 512672235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 103127496305362385168014480731999148700023240258166978457064154157093581670832 386
UVM_INFO @ 326479594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 39847709837681656289451271279029612905381176638650542144463737798853377819074 386
UVM_INFO @ 413222037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 21754291767094484339066988950396338239165124360848523256046029200253297353043 407
UVM_INFO @ 1593129860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 50933088668963188734644005076736141538647565576982306022064773557925618123244 386
UVM_INFO @ 462219545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 35894610302715723750820749266984168684689615573113742669567412810547466881175 386
UVM_INFO @ 502244013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 691573234208443149667991038837070787692261610338880906297233522886477893032 386
UVM_INFO @ 433257174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 106325840486450865091389066317452337261827908576754014513267002540479945148424 386
UVM_INFO @ 513214423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 53097196461171701534117026508666343447697063104623728353881192308580573412460 386
UVM_INFO @ 516759544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 27698321268178266915449104145836726765837825893421103299067039428846839562853 386
UVM_INFO @ 457875183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 20965750897584638012741528572426878516465194531033795983526604902799146331962 386
UVM_INFO @ 535792580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 82434204630074921238646126644166106442385941104066201970958738154182083491521 386
UVM_INFO @ 408323735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 65566625194746130740498265189235504703679391589369789780985177494613133250967 414
UVM_INFO @ 1713261579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 51411256161972579347503548664961830143326011120421347107674043568056874575716 387
UVM_INFO @ 806543790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 13559756292955018845334470400504814017391467229107212062013237868167986785638 386
UVM_INFO @ 340513199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 62311212342458685958008210918257631865986326145125362553916545785154722954130 386
UVM_INFO @ 386311828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 89204270469124807637226202496398559625991193452338337710772701367099866487049 386
UVM_INFO @ 324295819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 51561848558290349864982338988795227290966596998572839414692453691421673964514 386
UVM_INFO @ 314441057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 114506760322553809319797039457135886576647754687040966162614869687768049343970 386
UVM_INFO @ 292018680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 77433403749627918648695201353840635246560914785726875641095004647455275347783 386
UVM_INFO @ 521157357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 96519784621789353547181352711773175759079096128679263487931886398542488723989 386
UVM_INFO @ 278531799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 23588720700714414832643075080529056356508944090247350200149502117638427741043 386
UVM_INFO @ 414989561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 66980132629758078995546596915138690182197146884781260133355628993483924404603 469
UVM_INFO @ 33087513893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 18215755398386340087438030601128778928832814897618625593101470103476892355687 386
UVM_INFO @ 346296200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 16376935787511988584060841324314044439544121653962368959378495969720766122364 386
UVM_INFO @ 461773460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 95153741405627912200126813893921334075863512851985389092716793555073142216053 386
UVM_INFO @ 536400629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 64518149118023653950030030700553742510111339660156467847397422633024975742988 386
UVM_INFO @ 292398299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 88374100115750589688172006757054087712864002185212800685771398332022809649545 386
UVM_INFO @ 514265212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 54733977370367206213549373288475367206241816084892030031467092949955144790697 386
UVM_INFO @ 349717531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 76686016110807804200093368435584685540725519992414508184465375694217599087120 386
UVM_INFO @ 325495207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 28073990981429068611621532232982368989458629111965172992803141412639330623324 386
UVM_INFO @ 371528648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 30969145252491155232683954429938461954013230076264195222150890589523257418623 432
UVM_INFO @ 3176356576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 35456328077755239425085400994793386078227178491910317506750205479671145596600 386
UVM_INFO @ 514730313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 26226601424826319278976312816288264046551115564502379583515001992222192641110 386
UVM_INFO @ 457820642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 46199937069250451642888049172521873603836491247190489743335296078637512420031 386
UVM_INFO @ 450723563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 68250643927463046380205175546739740962693698692231240928864585714686790840653 386
UVM_INFO @ 517650176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 2535297267779594244401036316690990377001319376971331521842058273108724186892 386
UVM_INFO @ 506896150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 92172229170113285584942878590285943864722937154884614829721633761173660926065 386
UVM_INFO @ 309524860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 55101463736399734424661847640766218302719045251585128946031640232653818979877 386
UVM_INFO @ 478990503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 68253389858772039847031903733563144604233957752516353796694320084705466312709 386
UVM_INFO @ 353691986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 9413671193225498150768424911252268130122492358470021356822071150795581047350 399
UVM_INFO @ 873407396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 10044186945138225949972146516117881052099203852921069593472720989586781513651 391
UVM_INFO @ 12462903629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 54841151136789407782257949603751616848800949324743337534108681835874696358499 386
UVM_INFO @ 383951446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 98289842477093481937372715525339798480154843089542035711283612870108495448675 386
UVM_INFO @ 296980453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 43446576715458384402687751579024369390370924250822209174449526560031060050705 386
UVM_INFO @ 274422238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 40321544595935987185352273093295801851208866898565514451819921193225115905137 386
UVM_INFO @ 447191640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 18746175984189521964966423590822284591178712204628608137048388621370778326207 386
UVM_INFO @ 492554876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 17267602547395594561074664684643250976201117042539726155671771698148759194544 386
UVM_INFO @ 420525087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 62533916703999373098521920751050281215071356471322622146341183668691842596355 386
UVM_INFO @ 303185568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 91681388579834199426027804860970201210610136046631649927035715282002624740357 386
UVM_INFO @ 448521254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 113761499419721485554139596999930328025475644827288084053593555821293773855618 414
UVM_INFO @ 4932724406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 41284295058479666535893014409426876356076029661636494134875514124559188218383 414
UVM_INFO @ 113071778352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 92641548955723402446188077463470878516767551821198185632379207796984424890429 386
UVM_INFO @ 350333562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 46983429236985612187549675219864577927800764070270136120792082206015090655614 386
UVM_INFO @ 308227163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 54676368361519861064995442462819787591093733568636752521694596646646339461377 386
UVM_INFO @ 478959193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 47804281065681787887918262951141124340069355410103483433360988578314278832166 386
UVM_INFO @ 465651984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 72709171567284514546433562462727564589069362910072457329335813696346698541178 386
UVM_INFO @ 523538378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 32538669740606080461412153094524314703492667550191713173424553387142056760227 386
UVM_INFO @ 492163184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 29765762181493881943390606413950537771034084046520723197260100130088113847513 386
UVM_INFO @ 494368324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 36182800527385531190568582132218795060409178524190415340902121808039688819801 386
UVM_INFO @ 284062644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 97144564205037888525165448150460519375868839247626939660481933171902694803534 419
UVM_INFO @ 1935701017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 43245232316894023034290053964632182063293440237673421875499713626834204258531 387
UVM_INFO @ 872988525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 12013125872778730237542275034932345114428520829048447228024696998232395804903 386
UVM_INFO @ 502563820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 89496977262797176444579441798524532332795863691483481584398997036533367172793 386
UVM_INFO @ 447345747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 14358011409971173823200600172028008991365242803681611119038764879056949408669 386
UVM_INFO @ 388774975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 37983216759962507096079088417848500411759734290956092593176677198393109578060 386
UVM_INFO @ 273436017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 65077484674103189916756754571703434339424387456830436939646040965347081423089 386
UVM_INFO @ 508575385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 61960266323040483725070650866868778059178829411974746618901868709101003880171 386
UVM_INFO @ 440929232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 41077250880225029254632897428361518499415388262949050499357559795854958445541 386
UVM_INFO @ 346278991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 36752502465285115597708396899797999731698394244975191199814009393709718594523 386
UVM_INFO @ 391520111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 52406029697630464452663933597050698653100710726296662442436896423039001676927 392
UVM_INFO @ 705672926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 77809955495366714086297779498244181630183406074089659294274491567976821256330 387
UVM_INFO @ 907272348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---