| V1 |
|
100.00% |
| V2 |
|
88.95% |
| V2S |
|
98.54% |
| V3 |
|
60.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 49.950s | 1402.435us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_hw_reset | 10.150s | 114.306us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| alert_handler_csr_rw | 6.060s | 135.054us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| alert_handler_csr_bit_bash | 133.110s | 13425.806us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| alert_handler_csr_aliasing | 232.880s | 16633.628us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| alert_handler_csr_mem_rw_with_rand_reset | 11.410s | 266.968us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| alert_handler_csr_rw | 6.060s | 135.054us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 232.880s | 16633.628us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| esc_accum | 25 | 25 | 100.00 | |||
| alert_handler_esc_alert_accum | 281.120s | 25004.801us | 25 | 25 | 100.00 | |
| esc_timeout | 50 | 50 | 100.00 | |||
| alert_handler_esc_intr_timeout | 78.250s | 6293.267us | 50 | 50 | 100.00 | |
| entropy | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 3114.280s | 250353.711us | 25 | 25 | 100.00 | |
| sig_int_fail | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 60.750s | 4771.744us | 50 | 50 | 100.00 | |
| clk_skew | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 49.950s | 1402.435us | 10 | 10 | 100.00 | |
| random_alerts | 10 | 10 | 100.00 | |||
| alert_handler_random_alerts | 72.810s | 2853.218us | 10 | 10 | 100.00 | |
| random_classes | 50 | 50 | 100.00 | |||
| alert_handler_random_classes | 68.710s | 2854.803us | 50 | 50 | 100.00 | |
| ping_timeout | 17 | 50 | 34.00 | |||
| alert_handler_ping_timeout | 495.240s | 154439.500us | 17 | 50 | 34.00 | |
| lpg | 96 | 100 | 96.00 | |||
| alert_handler_lpg | 2889.850s | 992337.996us | 47 | 50 | 94.00 | |
| alert_handler_lpg_stub_clk | 2956.510s | 245870.980us | 49 | 50 | 98.00 | |
| stress_all | 50 | 50 | 100.00 | |||
| alert_handler_stress_all | 3700.620s | 159609.340us | 50 | 50 | 100.00 | |
| alert_handler_entropy_stress_test | 1 | 20 | 5.00 | |||
| alert_handler_entropy_stress | 26.370s | 723.534us | 1 | 20 | 5.00 | |
| alert_handler_alert_accum_saturation | 20 | 20 | 100.00 | |||
| alert_handler_alert_accum_saturation | 5.420s | 69.743us | 20 | 20 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| alert_handler_intr_test | 2.310s | 11.333us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 27.350s | 654.662us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 27.350s | 654.662us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 10.150s | 114.306us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 6.060s | 135.054us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 232.880s | 16633.628us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 37.880s | 638.461us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 10.150s | 114.306us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 6.060s | 135.054us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 232.880s | 16633.628us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 37.880s | 638.461us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 295.660s | 17261.812us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 295.660s | 17261.812us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 295.660s | 17261.812us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 295.660s | 17261.812us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors_with_csr_rw | 1136.010s | 126050.894us | 20 | 20 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| alert_handler_sec_cm | 27.500s | 498.000us | 5 | 5 | 100.00 | |
| alert_handler_tl_intg_err | 61.910s | 1995.099us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| alert_handler_tl_intg_err | 61.910s | 1995.099us | 25 | 25 | 100.00 | |
| sec_cm_config_shadow | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 295.660s | 17261.812us | 20 | 20 | 100.00 | |
| sec_cm_ping_timer_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 49.950s | 1402.435us | 10 | 10 | 100.00 | |
| sec_cm_alert_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 49.950s | 1402.435us | 10 | 10 | 100.00 | |
| sec_cm_alert_loc_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 49.950s | 1402.435us | 10 | 10 | 100.00 | |
| sec_cm_class_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 49.950s | 1402.435us | 10 | 10 | 100.00 | |
| sec_cm_alert_intersig_diff | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 60.750s | 4771.744us | 50 | 50 | 100.00 | |
| sec_cm_lpg_intersig_mubi | 47 | 50 | 94.00 | |||
| alert_handler_lpg | 2889.850s | 992337.996us | 47 | 50 | 94.00 | |
| sec_cm_esc_intersig_diff | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 60.750s | 4771.744us | 50 | 50 | 100.00 | |
| sec_cm_alert_rx_intersig_bkgn_chk | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 3114.280s | 250353.711us | 25 | 25 | 100.00 | |
| sec_cm_esc_tx_intersig_bkgn_chk | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 3114.280s | 250353.711us | 25 | 25 | 100.00 | |
| sec_cm_esc_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 27.500s | 498.000us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 27.500s | 498.000us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 27.500s | 498.000us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 27.500s | 498.000us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_global_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 27.500s | 498.000us | 5 | 5 | 100.00 | |
| sec_cm_accu_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 27.500s | 498.000us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 27.500s | 498.000us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 27.500s | 498.000us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_lfsr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 27.500s | 498.000us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 6 | 10 | 60.00 | |||
| alert_handler_stress_all_with_rand_reset | 310.220s | 3397.641us | 6 | 10 | 60.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state | 30 test runs | |||
| alert_handler_ping_timeout | 39826381535776977080488685302308466591881196871175577877487031699568171337431 | 124 |
UVM_INFO @ 27716094829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 31749049309647155366127809321313092306766532928978902802068607535558767057973 | 92 |
UVM_INFO @ 12113331038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 109606581556474545940592713674262162656983154881217439436760771522796420992323 | 143 |
UVM_INFO @ 12569204450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 59216093595667469906173637680737917977781162525809649045877790372454076061531 | 121 |
UVM_INFO @ 133071983348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 68937484858676308676945454027239151370766422606800073866595180326888373091519 | 84 |
UVM_INFO @ 2182668019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 82952395368474254679769281037591425629905563718360154895835719500736939357158 | 91 |
UVM_INFO @ 7179244215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 58843843223120646159773873241146408156488008208845641919249094393536126230678 | 114 |
UVM_INFO @ 7466762707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 41762942391588174286057520769133945470050609896722680816638614364146720017527 | 99 |
UVM_INFO @ 4915910541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 77258294067896971825717756020081282584632196905225224166312689293781779307605 | 99 |
UVM_INFO @ 5441151825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 49032009924905968129118467322673493601791712160975087998177654845051992824741 | 123 |
UVM_INFO @ 8376121460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 78411258505758433709019026539065412879710451894082748886305886882639962644917 | 84 |
UVM_INFO @ 6523225345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 55225361647174516992490498046531943347997001163285797212108112057768732160527 | 90 |
UVM_INFO @ 1338350411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 34122762348450190306107012174328763366354184969656667288942493154754066084525 | 84 |
UVM_INFO @ 4406849690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 70470970785694497966866895283310454492803831068194480594569810794154057183286 | 90 |
UVM_INFO @ 6279429942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 105966702740470701877493232089783513137497379205222448883161093031890703054617 | 99 |
UVM_INFO @ 21191789021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 56488692514052564939671892018483200063779209025289454118321641759042384537562 | 85 |
UVM_INFO @ 3745995716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 20658057961477363008978438842363264442169904591380337695965281702009774902609 | 114 |
UVM_INFO @ 4502047349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 115678014388908533726151313456227875662610423730747588110564595884080933078076 | 93 |
UVM_INFO @ 3306591031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 24683380917373463253471315062979416441651673739054747320008137565031451827746 | 108 |
UVM_INFO @ 15622477194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 26943070271649676177552477873061537719557996951203139038818707022559239931022 | 100 |
UVM_INFO @ 4446265539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 25192271721095584668998976659624289816194226232868222617363199471297755975253 | 118 |
UVM_INFO @ 32018404220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 26965472660069020916295755639521644348797373902806709608239770780897498408639 | 90 |
UVM_INFO @ 2067843265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 83822215305020337791923392630179677895229413104743002984584329380434503746081 | 117 |
UVM_INFO @ 35572806259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 31725365579348259262952866279170119316337534507578206258063814368369201006259 | 124 |
UVM_INFO @ 27937971160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 10705762995834390128931641957031559518246763466384895229262432053072067465417 | 93 |
UVM_INFO @ 28484988148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 66687132195554918029185346998199189123596165001470776503276983492445076909056 | 120 |
UVM_INFO @ 36023902595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 74830383438149699408459775710788194669515610740100593680672162853649636428416 | 102 |
UVM_INFO @ 15125404614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 56808799389217240213426172155153041405933513813558412400494806271546424278699 | 84 |
UVM_INFO @ 1664874813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 104078776472003613446324512705039922032729646015301240788655283235321364079288 | 90 |
UVM_INFO @ 5106429436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 110557390356443900650325726651924091025115386713825836687462492768231486449818 | 84 |
UVM_INFO @ 2531693316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped | 19 test runs | |||
| alert_handler_entropy_stress | 60576014120440200741163324811979522461269698717354963481024731552170841310731 | 184 |
UVM_INFO @ 109986263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 47773628025696104973193459669369431982464007215314948902785438506743971252478 | 194 |
UVM_INFO @ 862304354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 57978170112893272444469346706155709902024150136409666757651225838004157745107 | 166 |
UVM_INFO @ 92015993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 87290772843757564751836626378470605815302785798794658657503785227846815894999 | 186 |
UVM_INFO @ 115169117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 82541459889311383673287692908268347653733075394932552116419012542195913933296 | 202 |
UVM_INFO @ 1672520075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 85410559189672608684526082018248959792608415141096258925971200937379920367513 | 194 |
UVM_INFO @ 187421724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 53764848915133588139141271884145990217519679913761319783636969251542639919262 | 200 |
UVM_INFO @ 758524380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 9936911338473852846413234585928795999104093100469917937074588388378238276861 | 178 |
UVM_INFO @ 132199477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 84536368883658714603449950272041676002035709914627605821569434956633587128458 | 202 |
UVM_INFO @ 446627899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 97953521085131928496029919211138606453468211208696056234934037826270724499678 | 168 |
UVM_INFO @ 3776309348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 80751994883774585548197913564800015074642648641256793531361219246740274598958 | 200 |
UVM_INFO @ 723533652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 31697511999578281683308321280848899521722115546949287402282248077253828679503 | 132 |
UVM_INFO @ 154610816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 38908542543028095811349484500392850044516623249840029030969809223496542292862 | 162 |
UVM_INFO @ 384222722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 19436867965463414131755473720311668265355443591615252589375310913415535291021 | 198 |
UVM_INFO @ 322566391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 98552808122711142403018757767716636347096268230606723541599849167045571412286 | 202 |
UVM_INFO @ 478317456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 43915191701042334184052897503551129507493826942530352519104062756894653264049 | 188 |
UVM_INFO @ 81828799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 47891627162727907340732407827825884213722547454099852902741108722548311334835 | 202 |
UVM_INFO @ 319496524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 36392912059254024383373216929686374714867466910892142952291407500311817278242 | 202 |
UVM_INFO @ 129113449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_entropy_stress | 39257374225142047580622171420757932885475116846150099067194209146312035586529 | 192 |
UVM_INFO @ 269103002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 4 test runs | |||
| alert_handler_stress_all_with_rand_reset | 18619492566924661707060767826384728548382468269076316749212707747083012310864 | 83 |
UVM_INFO @ 325034269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_stress_all_with_rand_reset | 23182969194699529850537566382777304044368004256748609074942179516970282188886 | 107 |
UVM_INFO @ 3259006231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_stress_all_with_rand_reset | 58663578402113800776570513399283541852298334779421625353662984408775437711025 | 101 |
UVM_INFO @ 1065892334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_stress_all_with_rand_reset | 40011972250289912938838184321080794858486119358961526578913680386637336431193 | 114 |
UVM_INFO @ 5169430228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalAlertPingFail) | 3 test runs | |||
| alert_handler_lpg_stub_clk | 58261557735917255166120081208984283510394471146410783288447403718057671514327 | 81 |
UVM_INFO @ 286146799112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_lpg | 26056093124319861542902280301730068965102398196226638748327123054871155864575 | 83 |
UVM_INFO @ 105694832535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_lpg | 103453268977173342021537096236556690834749757915784915698105669352181517414018 | 82 |
UVM_INFO @ 13068199131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. | 3 test runs | |||
| alert_handler_ping_timeout | 46065765509291484503567243612139736043216476065490368711494485334685951873174 | 80 |
UVM_INFO @ 178581375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_ping_timeout | 26446230352954182993787325187663469564779968835644381441289318228737261626999 | 80 |
UVM_INFO @ 204137348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_ping_timeout | 66192721949023472699600372755461890551012856307342136738683848153853071567642 | 80 |
UVM_INFO @ 537275296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.loc_alert_cause_* | 1 test run | |||
| alert_handler_lpg | 1180667416427410827245219594440740592958668673643573094743099618567801157962 | 80 |
UVM_INFO @ 102770539749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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