Simulation Results

Simulation Results: clkmgr

20/06/2026 02:47:04 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
93.87 %

code
98.55 %

assert
95.76 %

func
87.31 %

line
99.07 %

branch
98.74 %

cond
95.77 %

toggle
99.19 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		75.86%
V3		100.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	clkmgr_smoke	1.530s	89.218us	10	10	100.00
csr_hw_reset				1	1	100.00
	clkmgr_csr_hw_reset	1.170s	31.463us	1	1	100.00
csr_rw				5	5	100.00
	clkmgr_csr_rw	1.230s	68.503us	5	5	100.00
csr_bit_bash				1	1	100.00
	clkmgr_csr_bit_bash	4.270s	330.966us	1	1	100.00
csr_aliasing				1	1	100.00
	clkmgr_csr_aliasing	2.870s	269.744us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	clkmgr_csr_mem_rw_with_rand_reset	1.960s	173.942us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	clkmgr_csr_rw	1.230s	68.503us	5	5	100.00
	clkmgr_csr_aliasing	2.870s	269.744us	1	1	100.00

127/127 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				10	10	100.00
	clkmgr_peri	1.250s	82.592us	10	10	100.00
trans_enables				10	10	100.00
	clkmgr_trans	1.650s	134.586us	10	10	100.00
extclk				10	10	100.00
	clkmgr_extclk	1.410s	104.031us	10	10	100.00
clk_status				10	10	100.00
	clkmgr_clk_status	1.310s	116.148us	10	10	100.00
jitter				10	10	100.00
	clkmgr_smoke	1.530s	89.218us	10	10	100.00
frequency				10	10	100.00
	clkmgr_frequency	17.030s	2118.014us	10	10	100.00
frequency_timeout				10	10	100.00
	clkmgr_frequency_timeout	19.320s	2422.532us	10	10	100.00
frequency_overflow				10	10	100.00
	clkmgr_frequency	17.030s	2118.014us	10	10	100.00
stress_all				10	10	100.00
	clkmgr_stress_all	47.340s	5977.202us	10	10	100.00
alert_test				10	10	100.00
	clkmgr_alert_test	1.310s	75.485us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	clkmgr_tl_errors	4.810s	704.146us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	clkmgr_tl_errors	4.810s	704.146us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	clkmgr_csr_hw_reset	1.170s	31.463us	1	1	100.00
	clkmgr_csr_rw	1.230s	68.503us	5	5	100.00
	clkmgr_csr_aliasing	2.870s	269.744us	1	1	100.00
	clkmgr_same_csr_outstanding	3.790s	885.869us	5	5	100.00
tl_d_partial_access				12	12	100.00
	clkmgr_csr_hw_reset	1.170s	31.463us	1	1	100.00
	clkmgr_csr_rw	1.230s	68.503us	5	5	100.00
	clkmgr_csr_aliasing	2.870s	269.744us	1	1	100.00
	clkmgr_same_csr_outstanding	3.790s	885.869us	5	5	100.00

V2S

110/145 passed

75.86 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				12	30	40.00
	clkmgr_sec_cm	35.250s	10087.347us	0	5	0.00
	clkmgr_tl_intg_err	57.600s	10171.724us	12	25	48.00
shadow_reg_update_error				13	20	65.00
	clkmgr_shadow_reg_errors	1028.330s	200000.000us	13	20	65.00
shadow_reg_read_clear_staged_value				13	20	65.00
	clkmgr_shadow_reg_errors	1028.330s	200000.000us	13	20	65.00
shadow_reg_storage_error				13	20	65.00
	clkmgr_shadow_reg_errors	1028.330s	200000.000us	13	20	65.00
shadowed_reset_glitch				13	20	65.00
	clkmgr_shadow_reg_errors	1028.330s	200000.000us	13	20	65.00
shadow_reg_update_error_with_csr_rw				11	20	55.00
	clkmgr_shadow_reg_errors_with_csr_rw	486.430s	200000.000us	11	20	55.00
sec_cm_bus_integrity				12	25	48.00
	clkmgr_tl_intg_err	57.600s	10171.724us	12	25	48.00
sec_cm_meas_clk_bkgn_chk				10	10	100.00
	clkmgr_frequency	17.030s	2118.014us	10	10	100.00
sec_cm_timeout_clk_bkgn_chk				10	10	100.00
	clkmgr_frequency_timeout	19.320s	2422.532us	10	10	100.00
sec_cm_meas_config_shadow				13	20	65.00
	clkmgr_shadow_reg_errors	1028.330s	200000.000us	13	20	65.00
sec_cm_idle_intersig_mubi				10	10	100.00
	clkmgr_idle_intersig_mubi	2.470s	365.463us	10	10	100.00
sec_cm_lc_ctrl_intersig_mubi				10	10	100.00
	clkmgr_lc_ctrl_intersig_mubi	1.780s	302.425us	10	10	100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi				10	10	100.00
	clkmgr_lc_clk_byp_req_intersig_mubi	1.360s	85.151us	10	10	100.00
sec_cm_clk_handshake_intersig_mubi				9	10	90.00
	clkmgr_clk_handshake_intersig_mubi	2.110s	269.214us	9	10	90.00
sec_cm_div_intersig_mubi				10	10	100.00
	clkmgr_div_intersig_mubi	1.350s	76.085us	10	10	100.00
sec_cm_jitter_config_mubi				5	5	100.00
	clkmgr_csr_rw	1.230s	68.503us	5	5	100.00
sec_cm_idle_ctr_redun				0	5	0.00
	clkmgr_sec_cm	35.250s	10087.347us	0	5	0.00
sec_cm_meas_config_regwen				5	5	100.00
	clkmgr_csr_rw	1.230s	68.503us	5	5	100.00
sec_cm_clk_ctrl_config_regwen				5	5	100.00
	clkmgr_csr_rw	1.230s	68.503us	5	5	100.00
prim_count_check				0	5	0.00
	clkmgr_sec_cm	35.250s	10087.347us	0	5	0.00

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
regwen				10	10	100.00
	clkmgr_regwen	6.510s	2286.251us	10	10	100.00
stress_all_with_rand_reset				10	10	100.00
	clkmgr_stress_all_with_rand_reset	75.190s	11030.571us	10	10	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault				15 test runs
	clkmgr_tl_intg_err	82090552786515738297831360897792568131013494931641725409493303968049742102244	139	UVM_INFO @ 10084649509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	52654512407268542706385666028187963652492646562160079067328064961921828435259	131	UVM_INFO @ 10129950900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	109160328205838938430695864115753262849058233679718449283418285060970546381916	112	UVM_INFO @ 10033415768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	4206626141795936400949877595720499466442086472944453130010305902224989097144	108	UVM_INFO @ 10087346764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	114182991255272314918228963273258924877958921664583022568651903654511462800888	109	UVM_INFO @ 10107358475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	29519340340926596152086507675106069565110547549971883134173652429167557639653	97	UVM_INFO @ 10115699531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	99140005202276038554339434734994590007518821306723696555881629377948944327107	90	UVM_INFO @ 10009198484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	86995490682351294815554176483188947714952216908017880204772655057934321265629	93	UVM_INFO @ 10008207657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	54436088439158275968935390621573593671045538382326491343461197197933062202324	116	UVM_INFO @ 10041229537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	64650466990752077825623767017888902535274326587273722729570465170291127044414	136	UVM_INFO @ 10188132070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	83258874995956970551775983863027163140494419914615101246168187371260115145257	189	UVM_INFO @ 10081186474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	73950307388447567248455990833372468130583341706921327401142249697524863223206	201	UVM_INFO @ 10171724241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	89377619369559000523276552500563211006785818364529866447419471962894792969172	96	UVM_INFO @ 10058972141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	70076787732263599187807181846274372823000968332527300202610328027185237232197	163	UVM_INFO @ 10253048808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	28738439685536310319397884522446950069701895123149547629925883726863167561859	211	UVM_INFO @ 10161776374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				8 test runs
	clkmgr_shadow_reg_errors	67408815052186608688678524316298015456552996804467733810225033606191096276577	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	56899127812233339268079042936305635058976055205673502376456063577789704456464	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	18199574289744066993571364055841463429620369640611048403448583403586860812783	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	43609530793411253463685795313084987329045214037604643730355176227899716263248	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	62579013870881695524865656714083733074466122911804851571053489104860870500807	76	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	39052940111916857150916948887299694028820407306870460730798540095053444766174	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	78971763009401433255616647311758155287261082622646136994409774485276616260758	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	113360854058367201250793723225944352867446108864512781318231159799636807951057	76	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [] vs [*]) fatal error fatal_fault does not trigger!				4 test runs
	clkmgr_shadow_reg_errors_with_csr_rw	76403126523470940857476129004418672676051830715285833123262185774337842235924	76	UVM_INFO @ 108822160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	70421368827376868440952812557370724246916951881881011584963679528881900233254	75	UVM_INFO @ 54888443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	37129412455217954062720441837037488779613147027462173076690994829798797348774	75	UVM_INFO @ 57038399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	9830246507895119459710997914222295092402024185348835173116444535547536113075	75	UVM_INFO @ 66574084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.				3 test runs
	clkmgr_sec_cm	108412021203575696140563803405108192693640784260884801604548427331430601712689	77	UVM_INFO @ 2658848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	2021523745715367831580323114639694487570350923667273783439357184149784185581	78	UVM_INFO @ 1870177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	19066342839947591653830436796679932898374878660550547861290439312961738716939	82	UVM_INFO @ 7974180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [] vs [*]) extclk_status mismatch				1 test run
	clkmgr_clk_handshake_intersig_mubi	37471907197972021534004775882302200525008576981765519877182301814448722408797	74	UVM_INFO @ 8019531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.clk_enables (addr=*)				1 test run
	clkmgr_shadow_reg_errors_with_csr_rw	64746243478637071664960067846718883973191630562297767208624892193798300739167	75	UVM_INFO @ 2039693828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.clk_hints_status (addr=*)				1 test run
	clkmgr_shadow_reg_errors_with_csr_rw	85127740639910606004937221240985888445712003034167234373509244391751488500685	75	UVM_INFO @ 2070656519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.fatal_err_code.shadow_storage_err reset value: Check_csr_read_clear_staged_val task: check storage_err status				1 test run
	clkmgr_shadow_reg_errors_with_csr_rw	16199439583634545723052829813440998049523066918150443521368947566554541779377	76	UVM_INFO @ 231942978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.extclk_ctrl_regwen (addr=*)				1 test run
	clkmgr_shadow_reg_errors_with_csr_rw	105576285702180779597590017572016516685921063937029076661712077443143479621924	76	UVM_INFO @ 2334693456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---