Simulation Results: csrng

 
20/06/2026 02:47:04 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.38 %
  • code
  • 96.17 %
  • assert
  • 97.16 %
  • func
  • 89.80 %
  • block
  • 98.49 %
  • line
  • 99.50 %
  • branch
  • 96.30 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
98.16%
V2S
99.07%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 25 25 100.00
csrng_smoke 9.000s 36.951us 25 25 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 32.000s 15.419us 1 1 100.00
csr_rw 5 5 100.00
csrng_csr_rw 32.000s 22.040us 5 5 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 53.000s 631.859us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 33.000s 80.064us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
csrng_csr_mem_rw_with_rand_reset 34.000s 206.501us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
csrng_csr_rw 32.000s 22.040us 5 5 100.00
csrng_csr_aliasing 33.000s 80.064us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 36.000s 459.942us 200 200 100.00
alerts 500 500 100.00
csrng_alert 61.000s 5402.255us 500 500 100.00
err 500 500 100.00
csrng_err 32.000s 25.640us 500 500 100.00
cmds 1 25 4.00
csrng_cmds 34.000s 91.949us 1 25 4.00
life cycle 1 25 4.00
csrng_cmds 34.000s 91.949us 1 25 4.00
stress_all 25 25 100.00
csrng_stress_all 978.000s 35099.736us 25 25 100.00
intr_test 10 10 100.00
csrng_intr_test 27.000s 46.979us 10 10 100.00
alert_test 10 10 100.00
csrng_alert_test 32.000s 18.902us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
csrng_tl_errors 20.000s 1384.024us 25 25 100.00
tl_d_illegal_access 25 25 100.00
csrng_tl_errors 20.000s 1384.024us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
csrng_csr_hw_reset 32.000s 15.419us 1 1 100.00
csrng_csr_rw 32.000s 22.040us 5 5 100.00
csrng_csr_aliasing 33.000s 80.064us 1 1 100.00
csrng_same_csr_outstanding 22.000s 169.335us 5 5 100.00
tl_d_partial_access 12 12 100.00
csrng_csr_hw_reset 32.000s 15.419us 1 1 100.00
csrng_csr_rw 32.000s 22.040us 5 5 100.00
csrng_csr_aliasing 33.000s 80.064us 1 1 100.00
csrng_same_csr_outstanding 22.000s 169.335us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
csrng_sec_cm 19.000s 79.787us 5 5 100.00
csrng_tl_intg_err 13.000s 1187.218us 25 25 100.00
sec_cm_config_regwen 18 30 60.00
csrng_regwen 24.000s 37.410us 13 25 52.00
csrng_csr_rw 32.000s 22.040us 5 5 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 61.000s 5402.255us 500 500 100.00
sec_cm_intersig_mubi 25 25 100.00
csrng_stress_all 978.000s 35099.736us 25 25 100.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 36.000s 459.942us 200 200 100.00
csrng_err 32.000s 25.640us 500 500 100.00
csrng_sec_cm 19.000s 79.787us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 36.000s 459.942us 200 200 100.00
csrng_err 32.000s 25.640us 500 500 100.00
csrng_sec_cm 19.000s 79.787us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 36.000s 459.942us 200 200 100.00
csrng_err 32.000s 25.640us 500 500 100.00
csrng_sec_cm 19.000s 79.787us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 36.000s 459.942us 200 200 100.00
csrng_err 32.000s 25.640us 500 500 100.00
csrng_sec_cm 19.000s 79.787us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 36.000s 459.942us 200 200 100.00
csrng_err 32.000s 25.640us 500 500 100.00
csrng_sec_cm 19.000s 79.787us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 61.000s 5402.255us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 36.000s 459.942us 200 200 100.00
csrng_err 32.000s 25.640us 500 500 100.00
sec_cm_constants_lc_gated 25 25 100.00
csrng_stress_all 978.000s 35099.736us 25 25 100.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 61.000s 5402.255us 500 500 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
csrng_tl_intg_err 13.000s 1187.218us 25 25 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 36.000s 459.942us 200 200 100.00
csrng_err 32.000s 25.640us 500 500 100.00
csrng_sec_cm 19.000s 79.787us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 36.000s 459.942us 200 200 100.00
csrng_err 32.000s 25.640us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 36.000s 459.942us 200 200 100.00
csrng_err 32.000s 25.640us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 36.000s 459.942us 200 200 100.00
csrng_err 32.000s 25.640us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 36.000s 459.942us 200 200 100.00
csrng_err 32.000s 25.640us 500 500 100.00
csrng_sec_cm 19.000s 79.787us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 36.000s 459.942us 200 200 100.00
csrng_err 32.000s 25.640us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
csrng_stress_all_with_rand_reset 3601.000s 0.000us 0 10 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 21 test runs
csrng_cmds 14257761479843276518551765923856822411624036378586305445006415205743743123583 100
UVM_INFO @ 91949163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 105472428107477691680821782465379561171171634745683076651102580099599744837959 100
UVM_INFO @ 87199989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 31197451247230245988904318495999619115204091717471024568530689641832583394764 100
UVM_INFO @ 60498503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 63130171451287825358498668154779974278558497393967172391436169848195465498450 100
UVM_INFO @ 60337356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 79472127027590895934354791875201073922972310362172819970171540560162394033289 100
UVM_INFO @ 277996133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 14073030854719995275808542126569592116532058288144659349705918811888026253364 100
UVM_INFO @ 140008930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 17379663320889276040356533353962575495592831172045444238999952032936594354729 100
UVM_INFO @ 54537359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 104921280036723161373281149847566550004555645724236666208033725684410875123470 100
UVM_INFO @ 19707816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 51915518037978442677728032140187501858400435943104264671100041913114992068948 100
UVM_INFO @ 140354290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 96966281354736434365219469017330671975230727159470722687295628275554890784591 100
UVM_INFO @ 284695824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 22081784347011550650332990028642776507762346193949793508153720460518379434969 100
UVM_INFO @ 287143824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 104119448679733081768414536456139156189334169225046165763533241180898986064183 100
UVM_INFO @ 389246683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 110782185548369620569064890202344938802004187700213255999072938362718281288794 120
UVM_INFO @ 1565011080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 110848043487020264870673947450784554624956440105074046301776769527445065944877 100
UVM_INFO @ 73908223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 104946813218490384522487674384811890224291096858273734902991935881780584243570 100
UVM_INFO @ 452748836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 107809098352045111148507037899062733829126630015267177553517353871677190204193 100
UVM_INFO @ 58062307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 21149510641973224474661782565772759878278893534573610109901639376924731819307 100
UVM_INFO @ 516600069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 113328070806412673385841202441994159944565860687359361293848434416746692958129 100
UVM_INFO @ 104081501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 61903559690471291205633595335979291547338298031963063700357735886419665594483 100
UVM_INFO @ 11724781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 59698422877295884185486833373110961252102998664222235452212079312483269634273 100
UVM_INFO @ 57018647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 29152672516370203199942929965353254838406629503923530943916654562813190006781 100
UVM_INFO @ 370149078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 9 test runs
csrng_regwen 1996767566141760167995352837352397177567089085743948160118987072325104431415 99
UVM_INFO @ 2791402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 110068627576993493742742431530537821732515638938455692821293914062815450038132 99
UVM_INFO @ 11345909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 56313702801052155294189409204861859322582065575309023717334109886126946867606 99
UVM_INFO @ 13117928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 110704307906315123412018970203976428888591355623065159947056863927810642127338 99
UVM_INFO @ 2482294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 38911249338762911136450620082122101085378381141607439972619140436702801024110 99
UVM_INFO @ 6255792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 43320110544742948530286676384806240265020403395202286402368267057477783180551 99
UVM_INFO @ 22327990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 73883282557295272668657447362737017281675908133554607929924873514011438423609 99
UVM_INFO @ 9846044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 94924034713739155068496986729209350362772354997768231364463323340440675889934 99
UVM_INFO @ 1651406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 32511754397593353491227600561771568020036787159085647489333284774281621738023 99
UVM_INFO @ 3983745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 8 test runs
csrng_stress_all_with_rand_reset 77913347602077996612203459966217803382721317642355410826262181647516157675453 None
csrng_stress_all_with_rand_reset 111336719614044986613532217801321059936384723012695829305693340508688055460348 None
csrng_stress_all_with_rand_reset 8202178608705477046975210537752702824686237661136833223293539921813165255194 None
csrng_stress_all_with_rand_reset 80424858594718451054293104782163288784451376207937432814246806194184682322727 None
csrng_stress_all_with_rand_reset 36884194714856369553499191677112032092516724952900138446706981356660726119905 None
csrng_stress_all_with_rand_reset 71084173305951921597903126057958239696769752867892588887781320971728016460656 None
csrng_stress_all_with_rand_reset 93422878017017841637711400112011334466357080808130209324534383795815527472357 None
csrng_stress_all_with_rand_reset 50573364358283185495278025583124330745025480583320420736512201923295626971746 None
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE 3 test runs
csrng_regwen 69647010576958135512415539543690466582567414278235306734775367798041655274693 99
UVM_INFO @ 7052174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 17833899097094789745763733398953586123130273337252993447753901513115592773586 99
UVM_INFO @ 7933663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 102577372441490858096195185152653179944311262865390269758510154258196651517076 99
UVM_INFO @ 5845138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:640) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [*] vs * [*]) 2 test runs
csrng_cmds 88485057073028395774252300943257490706457012264838073041370854858640558511344 109
UVM_INFO @ 101680967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 108456349817286555873647094990886752295461144702304387531389131132807828182266 109
UVM_INFO @ 196772889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_alert triggered unexpectedly 1 test run
csrng_cmds 77721912701483016176650364268995791513591333371963334340793576306236553178266 108
UVM_INFO @ 6620573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 1 test run
csrng_stress_all_with_rand_reset 17503592072074922787714559441548325628119909332999361036723544564169451179449 228
UVM_INFO @ 29586176636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started 1 test run
csrng_stress_all_with_rand_reset 52586011021640982739269822723325750641365629576297989622655157724039135023290 190
UVM_INFO @ 7983709562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---