Simulation Results: edn/edn0

 
20/06/2026 02:47:04 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.69 %
  • code
  • 95.74 %
  • assert
  • 98.48 %
  • func
  • 92.86 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.20 %
  • toggle
  • 97.12 %
  • FSM
  • 91.94 %
Validation stages
V1
100.00%
V2
98.68%
V2S
100.00%
V3
93.33%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.490s 70.977us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.580s 19.176us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.390s 37.665us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.280s 85.647us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.560s 94.309us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.870s 39.914us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.390s 37.665us 5 5 100.00
edn_csr_aliasing 1.560s 94.309us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 115.880s 11529.821us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 115.880s 11529.821us 100 100 100.00
genbits 100 100 100.00
edn_genbits 115.880s 11529.821us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.430s 25.418us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.910s 456.641us 200 200 100.00
errs 100 100 100.00
edn_err 1.680s 21.436us 100 100 100.00
disable 92 100 92.00
edn_disable 1.500s 12.449us 50 50 100.00
edn_disable_auto_req_mode 12.820s 500.000us 42 50 84.00
stress_all 30 30 100.00
edn_stress_all 7.910s 373.190us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.410s 23.917us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.530s 46.893us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 3.370s 356.908us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 3.370s 356.908us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.580s 19.176us 1 1 100.00
edn_csr_rw 1.390s 37.665us 5 5 100.00
edn_csr_aliasing 1.560s 94.309us 1 1 100.00
edn_same_csr_outstanding 1.610s 32.931us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.580s 19.176us 1 1 100.00
edn_csr_rw 1.390s 37.665us 5 5 100.00
edn_csr_aliasing 1.560s 94.309us 1 1 100.00
edn_same_csr_outstanding 1.610s 32.931us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 9.060s 6692.403us 5 5 100.00
edn_tl_intg_err 4.090s 321.743us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.410s 171.327us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.910s 456.641us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 9.060s 6692.403us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 9.060s 6692.403us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 9.060s 6692.403us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 9.060s 6692.403us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.910s 456.641us 200 200 100.00
edn_sec_cm 9.060s 6692.403us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.910s 456.641us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 4.090s 321.743us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 28 30 93.33
edn_stress_all_with_rand_reset 94.180s 78462.478us 28 30 93.33

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 6 test runs
edn_disable_auto_req_mode 79451547067866903824030296282380465022915150660761295789120623369940899566593 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 54875874045606505097703570665081356736795315024825117963920076149714758599569 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 80656306588844810820047676539364664262209575024785474873626588459388916240603 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 54155926995180961826242914732924288753816945704005696669885868371078399352232 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 4122085628945761546904184571067050419799807666773062020671874383250709009759 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 50614193690031186300810635110360973000517916784781780684988654008254403855061 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
edn_stress_all_with_rand_reset 11318557256155636324461808193395017836078345588273630545133076448197081022077 323
UVM_INFO @ 1449118514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 39065871268459665061443968327451605238316207401043093861714654676302688624080 137
UVM_INFO @ 621980603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:579) [scoreboard] Check failed (reqs_between_reseeds_ctr < max_num_reqs_between_reseeds) Maximum number of request between reseeds in auto_req_mode * exceeded. 1 test run
edn_disable_auto_req_mode 87748137054862892125463314595427597278744439833622074789031516209317129555327 89
UVM_INFO @ 38516027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 1 test run
edn_disable_auto_req_mode 16585550398859632861837053348318295974804706226730404581682393763275366935497 88
UVM_INFO @ 44306978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---