Simulation Results: edn/edn1

 
20/06/2026 02:47:04 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.43 %
  • code
  • 95.62 %
  • assert
  • 98.44 %
  • func
  • 92.23 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 94.62 %
  • toggle
  • 96.08 %
  • FSM
  • 94.32 %
Validation stages
V1
100.00%
V2
99.01%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.070s 49.121us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.810s 66.093us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.080s 36.636us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.570s 273.146us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.240s 156.865us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.640s 176.938us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.080s 36.636us 5 5 100.00
edn_csr_aliasing 1.240s 156.865us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 110.890s 9072.649us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 110.890s 9072.649us 100 100 100.00
genbits 100 100 100.00
edn_genbits 110.890s 9072.649us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.310s 33.498us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.540s 198.309us 200 200 100.00
errs 100 100 100.00
edn_err 1.340s 191.066us 100 100 100.00
disable 94 100 94.00
edn_disable 1.190s 13.189us 50 50 100.00
edn_disable_auto_req_mode 7.030s 500.000us 44 50 88.00
stress_all 30 30 100.00
edn_stress_all 7.530s 419.187us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.070s 11.668us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.170s 25.680us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 3.860s 150.019us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 3.860s 150.019us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 0.810s 66.093us 1 1 100.00
edn_csr_rw 1.080s 36.636us 5 5 100.00
edn_csr_aliasing 1.240s 156.865us 1 1 100.00
edn_same_csr_outstanding 1.420s 29.114us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 0.810s 66.093us 1 1 100.00
edn_csr_rw 1.080s 36.636us 5 5 100.00
edn_csr_aliasing 1.240s 156.865us 1 1 100.00
edn_same_csr_outstanding 1.420s 29.114us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 4.260s 418.383us 5 5 100.00
edn_tl_intg_err 2.810s 438.519us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 0.950s 27.750us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.540s 198.309us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.260s 418.383us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.260s 418.383us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 4.260s 418.383us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 4.260s 418.383us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.540s 198.309us 200 200 100.00
edn_sec_cm 4.260s 418.383us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.540s 198.309us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 2.810s 438.519us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 24 30 80.00
edn_stress_all_with_rand_reset 119.900s 102529.642us 24 30 80.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
edn_stress_all_with_rand_reset 38260394098271583180090649934542985782142649931721698072630005392353352499238 301
UVM_INFO @ 3132162358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 15283398044702889819925402820585107462551145650911031034546225896281401441456 178
UVM_INFO @ 1719588156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 54502215509232267529263978298232516671106826498168690515854821715457209713394 186
UVM_INFO @ 609564919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 19493861372779120346913536610372349730230104855031902956437898017632396352402 354
UVM_INFO @ 5227141188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 76903473623902881738221048772255933548895764092345898199820107841263457367330 178
UVM_INFO @ 1130674827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 4 test runs
edn_disable_auto_req_mode 964228567576307643194162683407706162817440170640742713979763052003210624257 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 31596849033039176689026879260796109327325957472111407828886061725774767804996 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 27212393564196163226635142616611418816326334653067463144716059001375662093177 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 89971941194983384750535999027113904911197367790181105346719215255188756579455 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *. 1 test run
edn_disable_auto_req_mode 30273676958461682389013086317497261849776883070554950981136635499353249312669 88
UVM_INFO @ 60134276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 1 test run
edn_stress_all_with_rand_reset 10536458851124763183846658972151235313817304828555643016330121890717995424142 342
UVM_INFO @ 14327755583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 1 test run
edn_disable_auto_req_mode 49889985638409768063750293077832440783794557048420670215477471247612722296437 88
UVM_INFO @ 96158186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---