Simulation Results

Simulation Results: flash_ctrl

20/06/2026 02:47:04 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
97.10 %

code
95.93 %

assert
96.94 %

func
98.42 %

line
96.12 %

branch
97.47 %

cond
94.90 %

toggle
98.66 %

FSM
92.52 %

Validation stages

V1		100.00%
V2		98.93%
V2S		99.16%
V3		100.00%
unmapped		100.00%

70/70 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	flash_ctrl_smoke	138.980s	25.623us	50	50	100.00
smoke_hw				5	5	100.00
	flash_ctrl_smoke_hw	28.320s	41.540us	5	5	100.00
csr_hw_reset				1	1	100.00
	flash_ctrl_csr_hw_reset	27.060s	72.560us	1	1	100.00
csr_rw				5	5	100.00
	flash_ctrl_csr_rw	16.120s	41.020us	5	5	100.00
csr_bit_bash				1	1	100.00
	flash_ctrl_csr_bit_bash	74.080s	1890.352us	1	1	100.00
csr_aliasing				1	1	100.00
	flash_ctrl_csr_aliasing	56.770s	16946.630us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	flash_ctrl_csr_mem_rw_with_rand_reset	18.120s	164.405us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	flash_ctrl_csr_rw	16.120s	41.020us	5	5	100.00
	flash_ctrl_csr_aliasing	56.770s	16946.630us	1	1	100.00
mem_walk				1	1	100.00
	flash_ctrl_mem_walk	6.960s	59.684us	1	1	100.00
mem_partial_access				1	1	100.00
	flash_ctrl_mem_partial_access	13.340s	39.403us	1	1	100.00

925/935 passed

98.93 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sw_op				5	5	100.00
	flash_ctrl_sw_op	23.890s	95.271us	5	5	100.00
host_read_direct				5	5	100.00
	flash_ctrl_host_dir_rd	92.770s	1414.776us	5	5	100.00
rma_hw_if				43	43	100.00
	flash_ctrl_hw_rma	1392.510s	149374.834us	3	3	100.00
	flash_ctrl_hw_rma_reset	880.440s	260271.495us	20	20	100.00
	flash_ctrl_lcmgr_intg	14.540s	50.585us	20	20	100.00
host_controller_arb				5	5	100.00
	flash_ctrl_host_ctrl_arb	1852.420s	308868.685us	5	5	100.00
erase_suspend				5	5	100.00
	flash_ctrl_erase_suspend	269.220s	3253.708us	5	5	100.00
program_reset				30	30	100.00
	flash_ctrl_prog_reset	181.410s	13397.428us	30	30	100.00
full_memory_access				5	5	100.00
	flash_ctrl_full_mem_access	5002.760s	1994564.562us	5	5	100.00
rd_buff_eviction				5	5	100.00
	flash_ctrl_rd_buff_evict	80.800s	1572.054us	5	5	100.00
rd_buff_eviction_w_ecc				101	105	96.19
	flash_ctrl_rw_evict	34.030s	31.834us	38	40	95.00
	flash_ctrl_rw_evict_all_en	34.280s	40.464us	38	40	95.00
	flash_ctrl_re_evict	32.620s	789.844us	25	25	100.00
host_arb				20	20	100.00
	flash_ctrl_phy_arb	305.650s	8228.134us	20	20	100.00
host_interleave				20	20	100.00
	flash_ctrl_phy_arb	305.650s	8228.134us	20	20	100.00
memory_protection				20	20	100.00
	flash_ctrl_mp_regions	644.290s	15142.784us	20	20	100.00
fetch_code				10	10	100.00
	flash_ctrl_fetch_code	27.700s	212.762us	10	10	100.00
all_partitions				20	20	100.00
	flash_ctrl_rand_ops	895.470s	3718.647us	20	20	100.00
error_mp				10	10	100.00
	flash_ctrl_error_mp	618.720s	112029.140us	10	10	100.00
error_prog_win				10	10	100.00
	flash_ctrl_error_prog_win	627.690s	14598.864us	10	10	100.00
error_prog_type				5	5	100.00
	flash_ctrl_error_prog_type	1460.820s	1650.303us	5	5	100.00
error_read_seed				20	20	100.00
	flash_ctrl_hw_read_seed_err	14.800s	42.993us	20	20	100.00
read_write_overflow				5	5	100.00
	flash_ctrl_oversize_error	158.460s	2435.215us	5	5	100.00
flash_ctrl_disable				50	50	100.00
	flash_ctrl_disable	24.700s	55.153us	50	50	100.00
flash_ctrl_connect				80	80	100.00
	flash_ctrl_connect	18.250s	17.056us	80	80	100.00
stress_all				5	5	100.00
	flash_ctrl_stress_all	914.730s	531.985us	5	5	100.00
secret_partition				130	130	100.00
	flash_ctrl_hw_sec_otp	157.130s	3193.196us	50	50	100.00
	flash_ctrl_otp_reset	135.050s	147.480us	80	80	100.00
isolation_partition				3	3	100.00
	flash_ctrl_hw_rma	1392.510s	149374.834us	3	3	100.00
interrupts				98	100	98.00
	flash_ctrl_intr_rd	195.770s	3081.269us	39	40	97.50
	flash_ctrl_intr_wr	2314.630s	500000.000us	9	10	90.00
	flash_ctrl_intr_rd_slow_flash	302.100s	17326.786us	40	40	100.00
	flash_ctrl_intr_wr_slow_flash	233.590s	181960.576us	10	10	100.00
invalid_op				20	20	100.00
	flash_ctrl_invalid_op	68.030s	4639.165us	20	20	100.00
mid_op_rst				5	5	100.00
	flash_ctrl_mid_op_rst	77.610s	1681.459us	5	5	100.00
double_bit_err				35	35	100.00
	flash_ctrl_read_word_sweep_derr	20.570s	31.807us	5	5	100.00
	flash_ctrl_ro_derr	140.880s	917.518us	10	10	100.00
	flash_ctrl_rw_derr	195.560s	8199.736us	10	10	100.00
	flash_ctrl_derr_detect	134.440s	1038.277us	5	5	100.00
	flash_ctrl_integrity	436.790s	21164.141us	5	5	100.00
single_bit_err				25	25	100.00
	flash_ctrl_read_word_sweep_serr	19.790s	73.611us	5	5	100.00
	flash_ctrl_ro_serr	124.530s	894.067us	10	10	100.00
	flash_ctrl_rw_serr	163.440s	2194.865us	10	10	100.00
singlebit_err_counter				5	5	100.00
	flash_ctrl_serr_counter	76.480s	12402.177us	5	5	100.00
singlebit_err_address				5	5	100.00
	flash_ctrl_serr_address	55.390s	1281.792us	5	5	100.00
scramble				59	62	95.16
	flash_ctrl_wo	2463.880s	200000.000us	18	20	90.00
	flash_ctrl_write_word_sweep	9.950s	31.724us	1	1	100.00
	flash_ctrl_read_word_sweep	13.250s	55.272us	1	1	100.00
	flash_ctrl_ro	103.400s	800.711us	20	20	100.00
	flash_ctrl_rw	3603.047s	0.000us	19	20	95.00
filesystem_support				4	5	80.00
	flash_ctrl_fs_sup	32.650s	578.550us	4	5	80.00
rma_write_process_error				23	23	100.00
	flash_ctrl_rma_err	911.620s	492962.886us	3	3	100.00
	flash_ctrl_hw_prog_rma_wipe_err	202.750s	10020.229us	20	20	100.00
alert_test				10	10	100.00
	flash_ctrl_alert_test	13.560s	47.275us	10	10	100.00
intr_test				10	10	100.00
	flash_ctrl_intr_test	13.600s	60.558us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	flash_ctrl_tl_errors	20.010s	250.718us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	flash_ctrl_tl_errors	20.010s	250.718us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	flash_ctrl_csr_hw_reset	27.060s	72.560us	1	1	100.00
	flash_ctrl_csr_rw	16.120s	41.020us	5	5	100.00
	flash_ctrl_csr_aliasing	56.770s	16946.630us	1	1	100.00
	flash_ctrl_same_csr_outstanding	21.090s	393.864us	5	5	100.00
tl_d_partial_access				12	12	100.00
	flash_ctrl_csr_hw_reset	27.060s	72.560us	1	1	100.00
	flash_ctrl_csr_rw	16.120s	41.020us	5	5	100.00
	flash_ctrl_csr_aliasing	56.770s	16946.630us	1	1	100.00
	flash_ctrl_same_csr_outstanding	21.090s	393.864us	5	5	100.00

V2S

471/475 passed

99.16 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	82.550s	227.248us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	flash_ctrl_shadow_reg_errors	82.550s	227.248us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	82.550s	227.248us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	flash_ctrl_shadow_reg_errors	82.550s	227.248us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	flash_ctrl_shadow_reg_errors_with_csr_rw	113.960s	294.862us	20	20	100.00
tl_intg_err				29	30	96.67
	flash_ctrl_sec_cm	2193.510s	2217.199us	4	5	80.00
	flash_ctrl_tl_intg_err	606.630s	710.458us	25	25	100.00
sec_cm_reg_bus_integrity				25	25	100.00
	flash_ctrl_tl_intg_err	606.630s	710.458us	25	25	100.00
sec_cm_host_bus_integrity				25	25	100.00
	flash_ctrl_tl_intg_err	606.630s	710.458us	25	25	100.00
sec_cm_mem_bus_integrity				6	6	100.00
	flash_ctrl_rd_intg	32.840s	76.470us	3	3	100.00
	flash_ctrl_wr_intg	13.940s	70.876us	3	3	100.00
sec_cm_scramble_key_sideload				50	50	100.00
	flash_ctrl_smoke	138.980s	25.623us	50	50	100.00
sec_cm_lc_ctrl_intersig_mubi				260	260	100.00
	flash_ctrl_otp_reset	135.050s	147.480us	80	80	100.00
	flash_ctrl_disable	24.700s	55.153us	50	50	100.00
	flash_ctrl_sec_info_access	76.570s	10451.081us	50	50	100.00
	flash_ctrl_connect	18.250s	17.056us	80	80	100.00
sec_cm_ctrl_config_regwen				5	5	100.00
	flash_ctrl_config_regwen	12.520s	29.738us	5	5	100.00
sec_cm_data_regions_config_regwen				5	5	100.00
	flash_ctrl_csr_rw	16.120s	41.020us	5	5	100.00
sec_cm_data_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	82.550s	227.248us	20	20	100.00
sec_cm_info_regions_config_regwen				5	5	100.00
	flash_ctrl_csr_rw	16.120s	41.020us	5	5	100.00
sec_cm_info_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	82.550s	227.248us	20	20	100.00
sec_cm_bank_config_regwen				5	5	100.00
	flash_ctrl_csr_rw	16.120s	41.020us	5	5	100.00
sec_cm_bank_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	82.550s	227.248us	20	20	100.00
sec_cm_mem_ctrl_global_esc				50	50	100.00
	flash_ctrl_disable	24.700s	55.153us	50	50	100.00
sec_cm_mem_ctrl_local_esc				6	6	100.00
	flash_ctrl_rd_intg	32.840s	76.470us	3	3	100.00
	flash_ctrl_access_after_disable	13.170s	97.625us	3	3	100.00
sec_cm_mem_addr_infection				3	3	100.00
	flash_ctrl_host_addr_infection	21.500s	46.055us	3	3	100.00
sec_cm_mem_disable_config_mubi				50	50	100.00
	flash_ctrl_disable	24.700s	55.153us	50	50	100.00
sec_cm_exec_config_redun				10	10	100.00
	flash_ctrl_fetch_code	27.700s	212.762us	10	10	100.00
sec_cm_mem_scramble				19	20	95.00
	flash_ctrl_rw	3603.047s	0.000us	19	20	95.00
sec_cm_mem_integrity				25	25	100.00
	flash_ctrl_rw_serr	163.440s	2194.865us	10	10	100.00
	flash_ctrl_rw_derr	195.560s	8199.736us	10	10	100.00
	flash_ctrl_integrity	436.790s	21164.141us	5	5	100.00
sec_cm_rma_entry_mem_sec_wipe				3	3	100.00
	flash_ctrl_hw_rma	1392.510s	149374.834us	3	3	100.00
sec_cm_ctrl_fsm_sparse				4	5	80.00
	flash_ctrl_sec_cm	2193.510s	2217.199us	4	5	80.00
sec_cm_phy_fsm_sparse				4	5	80.00
	flash_ctrl_sec_cm	2193.510s	2217.199us	4	5	80.00
sec_cm_phy_prog_fsm_sparse				4	5	80.00
	flash_ctrl_sec_cm	2193.510s	2217.199us	4	5	80.00
sec_cm_ctr_redun				4	5	80.00
	flash_ctrl_sec_cm	2193.510s	2217.199us	4	5	80.00
sec_cm_phy_arbiter_ctrl_redun				5	5	100.00
	flash_ctrl_phy_arb_redun	23.310s	922.885us	5	5	100.00
sec_cm_phy_host_grant_ctrl_consistency				3	5	60.00
	flash_ctrl_phy_host_grant_err	13.450s	52.029us	3	5	60.00
sec_cm_phy_ack_ctrl_consistency				5	5	100.00
	flash_ctrl_phy_ack_consistency	13.200s	53.148us	5	5	100.00
sec_cm_fifo_ctr_redun				4	5	80.00
	flash_ctrl_sec_cm	2193.510s	2217.199us	4	5	80.00
sec_cm_mem_tl_lc_gate_fsm_sparse				4	5	80.00
	flash_ctrl_sec_cm	2193.510s	2217.199us	4	5	80.00
sec_cm_prog_tl_lc_gate_fsm_sparse				4	5	80.00
	flash_ctrl_sec_cm	2193.510s	2217.199us	4	5	80.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
asymmetric_read_path				1	1	100.00
	flash_ctrl_rd_ooo	31.550s	479.244us	1	1	100.00

unmapped

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				3	3	100.00
	flash_ctrl_basic_rw	445.790s	765.959us	3	3	100.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ns hit, indicating a probable testbench issue				3 test runs
	flash_ctrl_wo	95627957044774090046671257210511293551910161822581678417800989383201234655534	108	UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_intr_wr	28052987617098604703159823261861294296588687186519005006165057628377886074606	108	UVM_INFO @ 500000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_wo	19954735783112907767744223658786340059583409213308612623474543668029137100338	108	UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'				2 test runs
	flash_ctrl_phy_host_grant_err	48454136067806536665047363578621885900617534394048057556801702885156020291569	125	UVM_ERROR @ 6371.3 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 6371.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_phy_host_grant_err	47941957049743761817713468862246193250452318577475984694625851194738682481135	125	UVM_ERROR @ 25561.0 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 25561.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value:				2 test runs
	flash_ctrl_rw_evict	61852253750519059040309166042902572641330804366721851881166541996753486017696	108	UVM_INFO @ 32455.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict	46458817458579804907043655037172271768658770002628148000253953832140804469603	108	UVM_INFO @ 54884.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.op_status.err reset value:				2 test runs
	flash_ctrl_rw_evict_all_en	90535294160440024805659792232131277007495639951846085083024611718847571294873	108	UVM_INFO @ 11569.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict_all_en	47660513363573953998023584240122100315489494402310928409162076352796318312427	108	UVM_INFO @ 50301.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (alert_receiver_driver.sv:262) driver [driver] m_transaction_tasks nonempty after reset: '{:}				1 test run
	flash_ctrl_sec_cm	21461774369070151523668287510346574900316639501847644970653992497304327676638	4950	UVM_INFO @ 1179349.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (flash_phy_prim_monitor.sv:44) [monitor] timeout waiting for mon_start				1 test run
	flash_ctrl_fs_sup	31648109995029937606199723982156243099393276843269094092432580989365196979507	108	UVM_INFO @ 500000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	flash_ctrl_rw	4091354347559198414367621293602850585390756921699610391173064473669238232763	None
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp c3f3dcdb_463b8e86:ffffffff_463b8e mismatch!!				1 test run
	flash_ctrl_intr_rd	61826009131913995647242797843300246493760397143107885429424578392347760275434	108	UVM_INFO @ 2610322.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---