Simulation Results: gpio

 
20/06/2026 02:47:04 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.66 %
  • code
  • 94.88 %
  • assert
  • 98.10 %
  • func
  • 100.00 %
  • line
  • 99.76 %
  • branch
  • 99.80 %
  • cond
  • 99.57 %
  • toggle
  • 80.38 %
Validation stages
V1
100.00%
V2
93.63%
V2S
100.00%
V3
35.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 40 40 100.00
gpio_smoke 1.500s 250.350us 10 10 100.00
gpio_smoke_no_pullup_pulldown 1.760s 129.843us 10 10 100.00
gpio_smoke_en_cdc_prim 1.730s 114.057us 10 10 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.400s 81.135us 10 10 100.00
csr_hw_reset 1 1 100.00
gpio_csr_hw_reset 0.940s 43.501us 1 1 100.00
csr_rw 5 5 100.00
gpio_csr_rw 0.970s 16.195us 5 5 100.00
csr_bit_bash 1 1 100.00
gpio_csr_bit_bash 3.050s 2676.879us 1 1 100.00
csr_aliasing 1 1 100.00
gpio_csr_aliasing 1.020s 91.234us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
gpio_csr_mem_rw_with_rand_reset 1.610s 152.912us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
gpio_csr_rw 0.970s 16.195us 5 5 100.00
gpio_csr_aliasing 1.020s 91.234us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
direct_and_masked_out 20 20 100.00
gpio_random_dout_din 1.640s 89.572us 10 10 100.00
gpio_random_dout_din_no_pullup_pulldown 1.760s 362.801us 10 10 100.00
out_in_regs_read_write 10 10 100.00
gpio_dout_din_regs_random_rw 1.260s 33.946us 10 10 100.00
gpio_interrupt_programming 10 10 100.00
gpio_intr_rand_pgm 1.730s 196.433us 10 10 100.00
random_interrupt_trigger 10 10 100.00
gpio_rand_intr_trigger 3.390s 666.385us 10 10 100.00
interrupt_and_noise_filter 10 10 100.00
gpio_intr_with_filter_rand_intr_event 2.720s 258.976us 10 10 100.00
noise_filter_stress 10 10 100.00
gpio_filter_stress 20.990s 578.699us 10 10 100.00
regs_long_reads_and_writes 10 10 100.00
gpio_random_long_reg_writes_reg_reads 5.880s 2588.232us 10 10 100.00
full_random 10 10 100.00
gpio_full_random 1.100s 251.456us 10 10 100.00
stress_all 0 10 0.00
gpio_stress_all 89.160s 27096.666us 0 10 0.00
alert_test 10 10 100.00
gpio_alert_test 0.920s 13.193us 10 10 100.00
intr_test 10 10 100.00
gpio_intr_test 0.950s 33.046us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
gpio_tl_errors 3.280s 706.601us 25 25 100.00
tl_d_illegal_access 25 25 100.00
gpio_tl_errors 3.280s 706.601us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
gpio_csr_rw 0.970s 16.195us 5 5 100.00
gpio_same_csr_outstanding 1.150s 68.507us 5 5 100.00
gpio_csr_aliasing 1.020s 91.234us 1 1 100.00
gpio_csr_hw_reset 0.940s 43.501us 1 1 100.00
tl_d_partial_access 12 12 100.00
gpio_csr_rw 0.970s 16.195us 5 5 100.00
gpio_same_csr_outstanding 1.150s 68.507us 5 5 100.00
gpio_csr_aliasing 1.020s 91.234us 1 1 100.00
gpio_csr_hw_reset 0.940s 43.501us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
gpio_tl_intg_err 1.740s 150.996us 25 25 100.00
gpio_sec_cm 1.290s 409.132us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
gpio_tl_intg_err 1.740s 150.996us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
straps_data 7 10 70.00
gpio_rand_straps 0.920s 13.121us 7 10 70.00
stress_all_with_rand_reset 0 10 0.00
gpio_stress_all_with_rand_reset 14.230s 671.285us 0 10 0.00

Error Messages

   Test seed line log context
UVM_ERROR (gpio_scoreboard.sv:216) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 13 test runs
gpio_stress_all 16699850823992890324091384724580544284810090734575159630099611476435076016241 77
UVM_INFO @ 908155756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 73543389375898542682778237606894560376963790418031760221339045629994077531329 75
UVM_INFO @ 5568479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 69951079177880030508577124432824787322317348042499313245347763496583191285712 343
UVM_INFO @ 872922660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 13043561752855500569318557333213729685048264007463934540610321063208025224845 279
UVM_INFO @ 1925950737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 84464870472239323324907045262368631237186812610669668091756182406774385973625 1078
UVM_INFO @ 17636222955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 27933219761203272303814278933271113264771944140994243632571995135407103504197 75
UVM_INFO @ 1333311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 43875089786871415587192524446855256521367183287595317087806444491733856135837 303
UVM_INFO @ 1914024812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 111594674479634777071646124848087325165615444581117520860517990621955398733418 75
UVM_INFO @ 6442436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 65204904330797881288789480913434600959320380070019823342865255483647770401914 75
UVM_INFO @ 2731534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 26848940729513489933746666848323424138216485483386983731492463857192637868460 224
UVM_INFO @ 1319506505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 8185880408960156972791375893635859177239920227802246098620109296415067710468 1880
UVM_INFO @ 27096665658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 74209876958949184369466741478172951289906361727481005674848611415816425562255 503
UVM_INFO @ 11421678667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 66899037837000081687170916936396106284401236296062639608769025365082246241239 1765
UVM_INFO @ 1893100232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [gpio_common_vseq] Check failed (vseq_done) 9 test runs
gpio_stress_all_with_rand_reset 31700665174721677994231487582672405024570334246673420133786057565985436892592 80
UVM_INFO @ 8786125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 66246649032507141278550333708671736778981639432432445709853218153329194422085 437
UVM_INFO @ 671285218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 35806749062907590283392327226711025155391715952293840255898694591506182652761 257
UVM_INFO @ 2026216960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 91938238514076556498395448854163215539359119383830613399118270683106114266562 215
UVM_INFO @ 2628114878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 71890142910214652544123170634657172578009628883660018863479798187511259283526 162
UVM_INFO @ 1863165931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 17336690557202382316533092215090171665277924787675994329267465032547622125495 81
UVM_INFO @ 17425289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 25803941397698708294154409377759050078126725173508860315722987626811796332596 171
UVM_INFO @ 1132718485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 41423437952964418393009326768509067830802737301404572760122870686595612322098 80
UVM_INFO @ 38969585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 14103023084034105661293195000377253304370569392461939227453841761642058691958 362
UVM_INFO @ 748868428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* 1 test run
gpio_stress_all_with_rand_reset 81521692639396065721393900555248549823202010845597034086065732231380361689157 82
UVM_INFO @ 38218356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---