Simulation Results: hmac

 
20/06/2026 02:47:04 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.61 %
  • code
  • 98.61 %
  • assert
  • 97.60 %
  • func
  • 99.62 %
  • line
  • 99.74 %
  • branch
  • 99.67 %
  • cond
  • 96.57 %
  • toggle
  • 100.00 %
  • FSM
  • 97.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 16.690s 3917.487us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.040s 115.764us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 1.080s 130.036us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 5.060s 1731.121us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.840s 715.212us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 690.940s 601810.899us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 1.080s 130.036us 5 5 100.00
hmac_csr_aliasing 2.840s 715.212us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 67.990s 8752.807us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 93.400s 11016.722us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 269.240s 42191.914us 30 30 100.00
hmac_test_sha384_vectors 548.260s 39757.023us 75 75 100.00
hmac_test_sha512_vectors 513.700s 20272.356us 75 75 100.00
hmac_test_hmac256_vectors 14.780s 1744.095us 50 50 100.00
hmac_test_hmac384_vectors 16.880s 1997.643us 60 60 100.00
hmac_test_hmac512_vectors 19.030s 2402.215us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 37.290s 1046.715us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1369.640s 10488.109us 10 10 100.00
error 10 10 100.00
hmac_error 162.780s 67182.510us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 124.160s 94113.816us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 16.690s 3917.487us 10 10 100.00
hmac_long_msg 67.990s 8752.807us 10 10 100.00
hmac_back_pressure 93.400s 11016.722us 25 25 100.00
hmac_datapath_stress 1369.640s 10488.109us 10 10 100.00
hmac_burst_wr 37.290s 1046.715us 50 50 100.00
hmac_stress_all 3392.260s 540487.772us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 16.690s 3917.487us 10 10 100.00
hmac_long_msg 67.990s 8752.807us 10 10 100.00
hmac_back_pressure 93.400s 11016.722us 25 25 100.00
hmac_datapath_stress 1369.640s 10488.109us 10 10 100.00
hmac_wipe_secret 124.160s 94113.816us 10 10 100.00
hmac_test_sha256_vectors 269.240s 42191.914us 30 30 100.00
hmac_test_sha384_vectors 548.260s 39757.023us 75 75 100.00
hmac_test_sha512_vectors 513.700s 20272.356us 75 75 100.00
hmac_test_hmac256_vectors 14.780s 1744.095us 50 50 100.00
hmac_test_hmac384_vectors 16.880s 1997.643us 60 60 100.00
hmac_test_hmac512_vectors 19.030s 2402.215us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 16.690s 3917.487us 10 10 100.00
hmac_long_msg 67.990s 8752.807us 10 10 100.00
hmac_back_pressure 93.400s 11016.722us 25 25 100.00
hmac_datapath_stress 1369.640s 10488.109us 10 10 100.00
hmac_burst_wr 37.290s 1046.715us 50 50 100.00
hmac_error 162.780s 67182.510us 10 10 100.00
hmac_wipe_secret 124.160s 94113.816us 10 10 100.00
hmac_test_sha256_vectors 269.240s 42191.914us 30 30 100.00
hmac_test_sha384_vectors 548.260s 39757.023us 75 75 100.00
hmac_test_sha512_vectors 513.700s 20272.356us 75 75 100.00
hmac_test_hmac256_vectors 14.780s 1744.095us 50 50 100.00
hmac_test_hmac384_vectors 16.880s 1997.643us 60 60 100.00
hmac_test_hmac512_vectors 19.030s 2402.215us 75 75 100.00
hmac_stress_all 3392.260s 540487.772us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 3392.260s 540487.772us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 0.910s 22.705us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 0.940s 20.216us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 4.940s 2180.529us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 4.940s 2180.529us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 1.040s 115.764us 1 1 100.00
hmac_csr_rw 1.080s 130.036us 5 5 100.00
hmac_csr_aliasing 2.840s 715.212us 1 1 100.00
hmac_same_csr_outstanding 2.910s 304.883us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 1.040s 115.764us 1 1 100.00
hmac_csr_rw 1.080s 130.036us 5 5 100.00
hmac_csr_aliasing 2.840s 715.212us 1 1 100.00
hmac_same_csr_outstanding 2.910s 304.883us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 1.380s 344.340us 5 5 100.00
hmac_tl_intg_err 5.030s 261.916us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 5.030s 261.916us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 16.690s 3917.487us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 8.040s 640.362us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 1001.780s 477385.533us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 4.270s 888.603us 1 1 100.00