Simulation Results: keymgr

 
20/06/2026 02:47:04 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.88 %
  • code
  • 98.85 %
  • assert
  • 97.72 %
  • func
  • 91.06 %
  • line
  • 99.20 %
  • branch
  • 99.00 %
  • cond
  • 98.24 %
  • toggle
  • 97.80 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.36%
V2S
99.08%
V3
65.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 30 30 100.00
keymgr_smoke 11.990s 2100.108us 30 30 100.00
random 30 30 100.00
keymgr_random 21.280s 1304.017us 30 30 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.220s 18.565us 1 1 100.00
csr_rw 5 5 100.00
keymgr_csr_rw 1.970s 63.318us 5 5 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 37.510s 6361.349us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 8.960s 321.723us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
keymgr_csr_mem_rw_with_rand_reset 2.050s 236.412us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
keymgr_csr_rw 1.970s 63.318us 5 5 100.00
keymgr_csr_aliasing 8.960s 321.723us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 62.740s 2045.721us 50 50 100.00
sideload 80 80 100.00
keymgr_sideload 21.530s 14705.914us 20 20 100.00
keymgr_sideload_kmac 6.430s 189.763us 20 20 100.00
keymgr_sideload_aes 9.070s 1326.168us 20 20 100.00
keymgr_sideload_otbn 24.930s 6709.620us 20 20 100.00
direct_to_disabled_state 30 30 100.00
keymgr_direct_to_disabled 12.650s 2784.063us 30 30 100.00
lc_disable 48 50 96.00
keymgr_lc_disable 7.230s 162.397us 48 50 96.00
kmac_error_response 20 20 100.00
keymgr_kmac_rsp_err 6.140s 1516.127us 20 20 100.00
invalid_sw_input 20 20 100.00
keymgr_sw_invalid_input 33.160s 4031.268us 20 20 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 20.650s 4369.361us 50 50 100.00
sync_async_fault_cross 18 20 90.00
keymgr_sync_async_fault_cross 10.680s 844.646us 18 20 90.00
stress_all 47 50 94.00
keymgr_stress_all 155.230s 31313.238us 47 50 94.00
intr_test 10 10 100.00
keymgr_intr_test 1.090s 18.147us 10 10 100.00
alert_test 10 10 100.00
keymgr_alert_test 1.210s 13.831us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
keymgr_tl_errors 5.230s 154.557us 25 25 100.00
tl_d_illegal_access 25 25 100.00
keymgr_tl_errors 5.230s 154.557us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
keymgr_csr_hw_reset 1.220s 18.565us 1 1 100.00
keymgr_csr_rw 1.970s 63.318us 5 5 100.00
keymgr_csr_aliasing 8.960s 321.723us 1 1 100.00
keymgr_same_csr_outstanding 3.250s 115.438us 5 5 100.00
tl_d_partial_access 12 12 100.00
keymgr_csr_hw_reset 1.220s 18.565us 1 1 100.00
keymgr_csr_rw 1.970s 63.318us 5 5 100.00
keymgr_csr_aliasing 8.960s 321.723us 1 1 100.00
keymgr_same_csr_outstanding 3.250s 115.438us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 36.680s 1899.505us 5 5 100.00
tl_intg_err 30 30 100.00
keymgr_sec_cm 36.680s 1899.505us 5 5 100.00
keymgr_tl_intg_err 11.660s 318.242us 25 25 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 5.430s 248.540us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 5.430s 248.540us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 5.430s 248.540us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 5.430s 248.540us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 16.270s 1109.382us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 36.680s 1899.505us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 36.680s 1899.505us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
keymgr_tl_intg_err 11.660s 318.242us 25 25 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 5.430s 248.540us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 62.740s 2045.721us 50 50 100.00
sec_cm_reseed_config_regwen 35 35 100.00
keymgr_random 21.280s 1304.017us 30 30 100.00
keymgr_csr_rw 1.970s 63.318us 5 5 100.00
sec_cm_sw_binding_config_regwen 35 35 100.00
keymgr_random 21.280s 1304.017us 30 30 100.00
keymgr_csr_rw 1.970s 63.318us 5 5 100.00
sec_cm_max_key_ver_config_regwen 35 35 100.00
keymgr_random 21.280s 1304.017us 30 30 100.00
keymgr_csr_rw 1.970s 63.318us 5 5 100.00
sec_cm_lc_ctrl_intersig_mubi 48 50 96.00
keymgr_lc_disable 7.230s 162.397us 48 50 96.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 20.650s 4369.361us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 20.650s 4369.361us 50 50 100.00
sec_cm_hw_key_sw_noaccess 30 30 100.00
keymgr_random 21.280s 1304.017us 30 30 100.00
sec_cm_output_keys_ctrl_redun 20 20 100.00
keymgr_sideload_protect 11.370s 677.978us 20 20 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 36.680s 1899.505us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 36.680s 1899.505us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 36.680s 1899.505us 5 5 100.00
sec_cm_ctrl_fsm_consistency 49 50 98.00
keymgr_custom_cm 19.420s 10405.965us 49 50 98.00
sec_cm_ctrl_fsm_global_esc 48 50 96.00
keymgr_lc_disable 7.230s 162.397us 48 50 96.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 36.680s 1899.505us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 36.680s 1899.505us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 36.680s 1899.505us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 49 50 98.00
keymgr_custom_cm 19.420s 10405.965us 49 50 98.00
sec_cm_kmac_if_done_ctrl_consistency 49 50 98.00
keymgr_custom_cm 19.420s 10405.965us 49 50 98.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 36.680s 1899.505us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 49 50 98.00
keymgr_custom_cm 19.420s 10405.965us 49 50 98.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 36.680s 1899.505us 5 5 100.00
sec_cm_ctrl_key_integrity 49 50 98.00
keymgr_custom_cm 19.420s 10405.965us 49 50 98.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 13 20 65.00
keymgr_stress_all_with_rand_reset 17.540s 2415.739us 13 20 65.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 7 test runs
keymgr_stress_all_with_rand_reset 23337699947782917844294861899806316343243803046271060556962791705609781147435 863
UVM_INFO @ 538088273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 67137969558292315979313493002764226894740499983518395537101664711284725347601 337
UVM_INFO @ 261477183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 8329133385309822187468395163779395926684377746172062103758933483615015256030 178
UVM_INFO @ 233049919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 109806787141295321202957421809000990507482332533694555716953608935397819329700 790
UVM_INFO @ 899999075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 53752452457836506069855445691117404862128679594551178502156427823593806987162 212
UVM_INFO @ 246921142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 53711598505422529263090910175024479291624773809936178159061879777562401729872 1603
UVM_INFO @ 395090045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 110104415836992127280316149113716188164770523057024851046622757489547928474025 293
UVM_INFO @ 131777680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_sync_async_fault_cross_vseq.sv:38) [keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] || act_fault_status[keymgr_pkg::FaultKmacOut] == * (* [*] vs * [*]) 2 test runs
keymgr_sync_async_fault_cross 40845535930397161195693383366779982082006552215834042088312713194872075943410 166
UVM_INFO @ 196364052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_sync_async_fault_cross 82425741504559089339815531257251899420841758979169487403844153833367197073339 138
UVM_INFO @ 323644698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share1_output_* 2 test runs
keymgr_stress_all 40593995411980856139488065425054391628427742518876726886143260133965464994265 93
UVM_INFO @ 126794588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all 40705291075274707277337583549284306676328977626073745750971524921196331794680 790
UVM_INFO @ 590035718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share0_output_* 2 test runs
keymgr_lc_disable 39305781836851508103340467495699125999150084101995452760876045087554639934778 216
UVM_INFO @ 53937567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_lc_disable 47836709335207194815356901234929783721127643588929963196318797006001840383700 348
UVM_INFO @ 92222351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* 1 test run
keymgr_stress_all 115772266124700648381541121303511825079571990494925173343820464627592229917739 4303
UVM_INFO @ 17185774164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (keymgr_custom_cm_vseq.sv:40) [keymgr_custom_cm_vseq] wait timeout occurred! 1 test run
keymgr_custom_cm 61516266798432191747755630403246499284504273620193106029650925849986856310092 128
UVM_INFO @ 10405964993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---