Simulation Results: lc_ctrl/volatile_unlock_disabled

 
20/06/2026 02:47:04 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.44 %
  • code
  • 85.92 %
  • assert
  • 94.97 %
  • func
  • 96.44 %
  • line
  • 97.28 %
  • branch
  • 94.00 %
  • cond
  • 81.84 %
  • toggle
  • 88.25 %
  • FSM
  • 68.22 %
Validation stages
V1
100.00%
V2
99.53%
V2S
100.00%
V3
20.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 4.560s 785.374us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.200s 20.273us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.530s 19.289us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.490s 85.093us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.530s 29.401us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.280s 34.152us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.530s 19.289us 5 5 100.00
lc_ctrl_csr_aliasing 1.530s 29.401us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 9.540s 83.164us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 15.390s 1362.852us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.280s 14.118us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 4.650s 105.110us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 18.320s 444.743us 20 20 100.00
lc_errors 19 20 95.00
lc_ctrl_errors 14.660s 1080.559us 19 20 95.00
security_escalation 138 140 98.57
lc_ctrl_state_failure 18.320s 444.743us 20 20 100.00
lc_ctrl_prog_failure 4.650s 105.110us 20 20 100.00
lc_ctrl_errors 14.660s 1080.559us 19 20 95.00
lc_ctrl_security_escalation 13.470s 1734.503us 20 20 100.00
lc_ctrl_jtag_state_failure 81.990s 4027.287us 20 20 100.00
lc_ctrl_jtag_prog_failure 19.600s 3408.325us 20 20 100.00
lc_ctrl_jtag_errors 65.880s 3270.894us 19 20 95.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 15.230s 7910.960us 20 20 100.00
lc_ctrl_jtag_state_post_trans 22.080s 769.170us 20 20 100.00
lc_ctrl_jtag_prog_failure 19.600s 3408.325us 20 20 100.00
lc_ctrl_jtag_errors 65.880s 3270.894us 19 20 95.00
lc_ctrl_jtag_access 19.620s 3540.353us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 40.940s 2808.713us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 5.750s 3206.908us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.160s 127.270us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 23.450s 10720.914us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 9.730s 2411.283us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.370s 49.369us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 6.500s 228.753us 10 10 100.00
lc_ctrl_jtag_alert_test 2.040s 143.373us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 20.880s 7330.624us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.600s 25.458us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 458.580s 31974.501us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.630s 24.941us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 3.750s 90.739us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 3.750s 90.739us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.200s 20.273us 1 1 100.00
lc_ctrl_csr_rw 1.530s 19.289us 5 5 100.00
lc_ctrl_csr_aliasing 1.530s 29.401us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.940s 198.405us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.200s 20.273us 1 1 100.00
lc_ctrl_csr_rw 1.530s 19.289us 5 5 100.00
lc_ctrl_csr_aliasing 1.530s 29.401us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.940s 198.405us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 9.070s 768.096us 5 5 100.00
lc_ctrl_tl_intg_err 4.230s 311.755us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 4.230s 311.755us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 15.390s 1362.852us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 18.320s 444.743us 20 20 100.00
lc_ctrl_sec_cm 9.070s 768.096us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 18.320s 444.743us 20 20 100.00
lc_ctrl_sec_cm 9.070s 768.096us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 18.320s 444.743us 20 20 100.00
lc_ctrl_sec_cm 9.070s 768.096us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 18.320s 444.743us 20 20 100.00
lc_ctrl_sec_cm 9.070s 768.096us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 18.320s 444.743us 20 20 100.00
lc_ctrl_sec_cm 9.070s 768.096us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 18.320s 444.743us 20 20 100.00
lc_ctrl_sec_cm 9.070s 768.096us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 18.320s 444.743us 20 20 100.00
lc_ctrl_sec_cm 9.070s 768.096us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 18.320s 444.743us 20 20 100.00
lc_ctrl_sec_cm 9.070s 768.096us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 13.470s 1734.503us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 9.540s 83.164us 20 20 100.00
lc_ctrl_jtag_state_post_trans 22.080s 769.170us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 13.380s 897.684us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 13.380s 897.684us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 15.780s 2431.290us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 9.990s 504.724us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 9.990s 504.724us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 10 20.00
lc_ctrl_stress_all_with_rand_reset 71.020s 2749.563us 2 10 20.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 8 test runs
lc_ctrl_stress_all_with_rand_reset 93031474371366324540355086951535953901826909279462577104804901904691460921507 2302
UVM_INFO @ 8640990918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 98061386988452085968240619987289246109630744757214285776717433500102514645589 166
UVM_INFO @ 102914543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 93986296817804667962246008587577196938304181824946956386357016966303216301037 1650
UVM_INFO @ 5781419857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 82531217886001809970252567005558224340238052585600937717139837855806078973895 1485
UVM_INFO @ 5617360829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 70539268369056852162375380328571785696949234335737410873508522987488311349869 8199
UVM_INFO @ 2749563370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 3700734863964097038153621735221941941811985689213326108047233262442171460293 2089
UVM_INFO @ 3370484070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 64435609443053771751655209813278292649511725029776615306306140320627502687438 194
UVM_INFO @ 3588064166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 18944869996597778292548500212341319721569710469191254872658624259158999249036 531
UVM_INFO @ 5235630497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 2 test runs
lc_ctrl_errors 109566897065852582488967775899740071727823384445371512786857215645302124601358 2704
UVM_INFO @ 1915924020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 63485283715108177156105795609072865776263825338404898264806843104681042044538 1488
UVM_INFO @ 2675850694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---