Simulation Results: lc_ctrl/volatile_unlock_enabled

 
20/06/2026 02:47:04 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.18 %
  • code
  • 85.75 %
  • assert
  • 94.69 %
  • func
  • 96.09 %
  • line
  • 97.26 %
  • branch
  • 93.80 %
  • cond
  • 81.20 %
  • toggle
  • 88.25 %
  • FSM
  • 68.22 %
Validation stages
V1
100.00%
V2
99.30%
V2S
100.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 6.590s 206.560us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.430s 39.370us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.300s 19.159us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.640s 85.694us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.600s 242.622us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.290s 97.131us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.300s 19.159us 5 5 100.00
lc_ctrl_csr_aliasing 1.600s 242.622us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 8.580s 262.596us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 14.510s 353.090us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.300s 13.265us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 6.070s 164.849us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 13.490s 1310.421us 20 20 100.00
lc_errors 18 20 90.00
lc_ctrl_errors 15.980s 1481.689us 18 20 90.00
security_escalation 138 140 98.57
lc_ctrl_state_failure 13.490s 1310.421us 20 20 100.00
lc_ctrl_prog_failure 6.070s 164.849us 20 20 100.00
lc_ctrl_errors 15.980s 1481.689us 18 20 90.00
lc_ctrl_security_escalation 13.810s 521.360us 20 20 100.00
lc_ctrl_jtag_state_failure 70.710s 3476.993us 20 20 100.00
lc_ctrl_jtag_prog_failure 13.810s 718.041us 20 20 100.00
lc_ctrl_jtag_errors 72.820s 36599.403us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 7.720s 5577.515us 20 20 100.00
lc_ctrl_jtag_state_post_trans 25.610s 2132.482us 20 20 100.00
lc_ctrl_jtag_prog_failure 13.810s 718.041us 20 20 100.00
lc_ctrl_jtag_errors 72.820s 36599.403us 20 20 100.00
lc_ctrl_jtag_access 20.940s 13120.285us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 32.080s 1549.474us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.960s 622.830us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.520s 182.069us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 41.680s 2645.189us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 19.700s 4260.930us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.320s 48.545us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 5.480s 389.468us 10 10 100.00
lc_ctrl_jtag_alert_test 1.890s 82.534us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 29.480s 3216.593us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.400s 31.775us 10 10 100.00
stress_all 9 10 90.00
lc_ctrl_stress_all 176.630s 12810.463us 9 10 90.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.530s 22.054us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.800s 1713.103us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.800s 1713.103us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.430s 39.370us 1 1 100.00
lc_ctrl_csr_rw 1.300s 19.159us 5 5 100.00
lc_ctrl_csr_aliasing 1.600s 242.622us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.830s 23.200us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.430s 39.370us 1 1 100.00
lc_ctrl_csr_rw 1.300s 19.159us 5 5 100.00
lc_ctrl_csr_aliasing 1.600s 242.622us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.830s 23.200us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 11.820s 868.946us 5 5 100.00
lc_ctrl_tl_intg_err 4.220s 269.085us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 4.220s 269.085us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 14.510s 353.090us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 13.490s 1310.421us 20 20 100.00
lc_ctrl_sec_cm 11.820s 868.946us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 13.490s 1310.421us 20 20 100.00
lc_ctrl_sec_cm 11.820s 868.946us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 13.490s 1310.421us 20 20 100.00
lc_ctrl_sec_cm 11.820s 868.946us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 13.490s 1310.421us 20 20 100.00
lc_ctrl_sec_cm 11.820s 868.946us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 13.490s 1310.421us 20 20 100.00
lc_ctrl_sec_cm 11.820s 868.946us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 13.490s 1310.421us 20 20 100.00
lc_ctrl_sec_cm 11.820s 868.946us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 13.490s 1310.421us 20 20 100.00
lc_ctrl_sec_cm 11.820s 868.946us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 13.490s 1310.421us 20 20 100.00
lc_ctrl_sec_cm 11.820s 868.946us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 13.810s 521.360us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 8.580s 262.596us 20 20 100.00
lc_ctrl_jtag_state_post_trans 25.610s 2132.482us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 13.560s 2201.506us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 13.560s 2201.506us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 11.760s 802.222us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 10.100s 432.489us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 10.100s 432.489us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
lc_ctrl_stress_all_with_rand_reset 53.930s 4480.294us 4 10 40.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
lc_ctrl_stress_all_with_rand_reset 52285396412690855847459070493182326003723456793714337633221263572133635457394 8350
UVM_INFO @ 2844058737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 1421780198981268444030854945901102602688341355669044159012104270157224767153 154
UVM_INFO @ 600218516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 22233216007889172757543577557550608622494434532218995648503812197580772445914 869
UVM_INFO @ 345941963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 92992352013067722297552837724841386856138489824582888062931479499196522137873 1752
UVM_INFO @ 2001105579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 5009757629804548740842505570073647786463769447576561362621758469445863146702 1347
UVM_INFO @ 861662400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 3 test runs
lc_ctrl_stress_all 20963355905577058676795480352308742151290144454957468192417343990858932755872 15929
UVM_INFO @ 33989987479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 115635411261877528318380030348191432672494492712449574011678985234473131932763 2074
UVM_INFO @ 208993892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 22371733140361266670379563224361498812421612611680214876419725912955190766614 1730
UVM_INFO @ 353295009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:923) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 1 test run
lc_ctrl_stress_all_with_rand_reset 69597317472490623713610566433588557916678359384675293664510086962462677271257 7897
UVM_INFO @ 4480293771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---