Simulation Results

Simulation Results: otbn

20/06/2026 02:47:04 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
95.73 %

code
95.91 %

assert
91.29 %

func
100.00 %

block
99.47 %

line
99.59 %

branch
93.25 %

toggle
93.24 %

FSM
97.56 %

Validation stages

V1		99.14%
V2		97.55%
V2S		96.35%
V3		40.00%
unmapped		100.00%

115/116 passed

99.14 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	otbn_smoke	32.000s	109.967us	1	1	100.00
single_binary				99	100	99.00
	otbn_single	68.000s	527.738us	99	100	99.00
csr_hw_reset				1	1	100.00
	otbn_csr_hw_reset	33.000s	17.995us	1	1	100.00
csr_rw				5	5	100.00
	otbn_csr_rw	33.000s	72.829us	5	5	100.00
csr_bit_bash				1	1	100.00
	otbn_csr_bit_bash	34.000s	93.479us	1	1	100.00
csr_aliasing				1	1	100.00
	otbn_csr_aliasing	33.000s	49.640us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	otbn_csr_mem_rw_with_rand_reset	36.000s	59.133us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	otbn_csr_rw	33.000s	72.829us	5	5	100.00
	otbn_csr_aliasing	33.000s	49.640us	1	1	100.00
mem_walk				1	1	100.00
	otbn_mem_walk	100.000s	2798.469us	1	1	100.00
mem_partial_access				1	1	100.00
	otbn_mem_partial_access	57.000s	580.713us	1	1	100.00

159/163 passed

97.55 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
reset_recovery				10	10	100.00
	otbn_reset	65.000s	166.442us	10	10	100.00
multi_error				1	1	100.00
	otbn_multi_err	78.000s	762.931us	1	1	100.00
back_to_back				8	10	80.00
	otbn_multi	89.000s	174.748us	8	10	80.00
stress_all				10	10	100.00
	otbn_stress_all	148.000s	744.578us	10	10	100.00
lc_escalation				58	60	96.67
	otbn_escalate	40.000s	26.815us	58	60	96.67
zero_state_err_urnd				5	5	100.00
	otbn_zero_state_err_urnd	11.000s	42.278us	5	5	100.00
sw_errs_fatal_chk				10	10	100.00
	otbn_sw_errs_fatal_chk	17.000s	18.360us	10	10	100.00
alert_test				10	10	100.00
	otbn_alert_test	34.000s	20.533us	10	10	100.00
intr_test				10	10	100.00
	otbn_intr_test	33.000s	24.775us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	otbn_tl_errors	13.000s	86.349us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	otbn_tl_errors	13.000s	86.349us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	otbn_csr_hw_reset	33.000s	17.995us	1	1	100.00
	otbn_csr_rw	33.000s	72.829us	5	5	100.00
	otbn_csr_aliasing	33.000s	49.640us	1	1	100.00
	otbn_same_csr_outstanding	27.000s	16.113us	5	5	100.00
tl_d_partial_access				12	12	100.00
	otbn_csr_hw_reset	33.000s	17.995us	1	1	100.00
	otbn_csr_rw	33.000s	72.829us	5	5	100.00
	otbn_csr_aliasing	33.000s	49.640us	1	1	100.00
	otbn_same_csr_outstanding	27.000s	16.113us	5	5	100.00

V2S

317/329 passed

96.35 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
mem_integrity				25	25	100.00
	otbn_imem_err	38.000s	84.682us	10	10	100.00
	otbn_dmem_err	33.000s	116.165us	15	15	100.00
internal_integrity				16	17	94.12
	otbn_alu_bignum_mod_err	38.000s	99.214us	5	5	100.00
	otbn_controller_ispr_rdata_err	37.000s	1029.778us	4	5	80.00
	otbn_mac_bignum_acc_err	37.000s	315.561us	5	5	100.00
	otbn_urnd_err	6.000s	16.673us	2	2	100.00
illegal_bus_access				5	5	100.00
	otbn_illegal_mem_acc	35.000s	16.298us	5	5	100.00
otbn_mem_gnt_acc_err				2	2	100.00
	otbn_mem_gnt_acc_err	34.000s	12.885us	2	2	100.00
otbn_non_sec_partial_wipe				7	10	70.00
	otbn_partial_wipe	33.000s	24.684us	7	10	70.00
tl_intg_err				30	30	100.00
	otbn_sec_cm	328.000s	5371.118us	5	5	100.00
	otbn_tl_intg_err	53.000s	387.670us	25	25	100.00
passthru_mem_tl_intg_err				2	5	40.00
	otbn_passthru_mem_tl_intg_err	52.000s	1238.264us	2	5	40.00
prim_fsm_check				5	5	100.00
	otbn_sec_cm	328.000s	5371.118us	5	5	100.00
prim_count_check				5	5	100.00
	otbn_sec_cm	328.000s	5371.118us	5	5	100.00
sec_cm_mem_scramble				1	1	100.00
	otbn_smoke	32.000s	109.967us	1	1	100.00
sec_cm_data_mem_integrity				15	15	100.00
	otbn_dmem_err	33.000s	116.165us	15	15	100.00
sec_cm_instruction_mem_integrity				10	10	100.00
	otbn_imem_err	38.000s	84.682us	10	10	100.00
sec_cm_bus_integrity				25	25	100.00
	otbn_tl_intg_err	53.000s	387.670us	25	25	100.00
sec_cm_controller_fsm_global_esc				58	60	96.67
	otbn_escalate	40.000s	26.815us	58	60	96.67
sec_cm_controller_fsm_local_esc				40	40	100.00
	otbn_imem_err	38.000s	84.682us	10	10	100.00
	otbn_dmem_err	33.000s	116.165us	15	15	100.00
	otbn_zero_state_err_urnd	11.000s	42.278us	5	5	100.00
	otbn_illegal_mem_acc	35.000s	16.298us	5	5	100.00
	otbn_sec_cm	328.000s	5371.118us	5	5	100.00
sec_cm_controller_fsm_sparse				5	5	100.00
	otbn_sec_cm	328.000s	5371.118us	5	5	100.00
sec_cm_scramble_key_sideload				99	100	99.00
	otbn_single	68.000s	527.738us	99	100	99.00
sec_cm_scramble_ctrl_fsm_local_esc				40	40	100.00
	otbn_imem_err	38.000s	84.682us	10	10	100.00
	otbn_dmem_err	33.000s	116.165us	15	15	100.00
	otbn_zero_state_err_urnd	11.000s	42.278us	5	5	100.00
	otbn_illegal_mem_acc	35.000s	16.298us	5	5	100.00
	otbn_sec_cm	328.000s	5371.118us	5	5	100.00
sec_cm_scramble_ctrl_fsm_sparse				5	5	100.00
	otbn_sec_cm	328.000s	5371.118us	5	5	100.00
sec_cm_start_stop_ctrl_fsm_global_esc				58	60	96.67
	otbn_escalate	40.000s	26.815us	58	60	96.67
sec_cm_start_stop_ctrl_fsm_local_esc				40	40	100.00
	otbn_imem_err	38.000s	84.682us	10	10	100.00
	otbn_dmem_err	33.000s	116.165us	15	15	100.00
	otbn_zero_state_err_urnd	11.000s	42.278us	5	5	100.00
	otbn_illegal_mem_acc	35.000s	16.298us	5	5	100.00
	otbn_sec_cm	328.000s	5371.118us	5	5	100.00
sec_cm_start_stop_ctrl_fsm_sparse				5	5	100.00
	otbn_sec_cm	328.000s	5371.118us	5	5	100.00
sec_cm_data_reg_sw_sca				99	100	99.00
	otbn_single	68.000s	527.738us	99	100	99.00
sec_cm_ctrl_redun				12	12	100.00
	otbn_ctrl_redun	40.000s	46.800us	12	12	100.00
sec_cm_pc_ctrl_flow_redun				5	5	100.00
	otbn_pc_ctrl_flow_redun	31.000s	44.206us	5	5	100.00
sec_cm_rnd_bus_consistency				5	5	100.00
	otbn_rnd_sec_cm	84.000s	274.016us	5	5	100.00
sec_cm_rnd_rng_digest				5	5	100.00
	otbn_rnd_sec_cm	84.000s	274.016us	5	5	100.00
sec_cm_rf_base_data_reg_sw_integrity				10	10	100.00
	otbn_rf_base_intg_err	34.000s	28.045us	10	10	100.00
sec_cm_rf_base_data_reg_sw_glitch_detect				5	5	100.00
	otbn_sec_cm	328.000s	5371.118us	5	5	100.00
sec_cm_stack_wr_ptr_ctr_redun				5	5	100.00
	otbn_sec_cm	328.000s	5371.118us	5	5	100.00
sec_cm_rf_bignum_data_reg_sw_integrity				10	10	100.00
	otbn_rf_bignum_intg_err	33.000s	65.019us	10	10	100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect				5	5	100.00
	otbn_sec_cm	328.000s	5371.118us	5	5	100.00
sec_cm_loop_stack_ctr_redun				5	5	100.00
	otbn_sec_cm	328.000s	5371.118us	5	5	100.00
sec_cm_loop_stack_addr_integrity				5	5	100.00
	otbn_stack_addr_integ_chk	24.000s	57.698us	5	5	100.00
sec_cm_call_stack_addr_integrity				5	5	100.00
	otbn_stack_addr_integ_chk	24.000s	57.698us	5	5	100.00
sec_cm_start_stop_ctrl_state_consistency				7	7	100.00
	otbn_sec_wipe_err	48.000s	426.743us	7	7	100.00
sec_cm_data_mem_sec_wipe				99	100	99.00
	otbn_single	68.000s	527.738us	99	100	99.00
sec_cm_instruction_mem_sec_wipe				99	100	99.00
	otbn_single	68.000s	527.738us	99	100	99.00
sec_cm_data_reg_sw_sec_wipe				99	100	99.00
	otbn_single	68.000s	527.738us	99	100	99.00
sec_cm_write_mem_integrity				8	10	80.00
	otbn_multi	89.000s	174.748us	8	10	80.00
sec_cm_ctrl_flow_count				99	100	99.00
	otbn_single	68.000s	527.738us	99	100	99.00
sec_cm_ctrl_flow_sca				99	100	99.00
	otbn_single	68.000s	527.738us	99	100	99.00
sec_cm_data_mem_sw_noaccess				5	5	100.00
	otbn_sw_no_acc	15.000s	54.135us	5	5	100.00
sec_cm_key_sideload				99	100	99.00
	otbn_single	68.000s	527.738us	99	100	99.00
sec_cm_tlul_fifo_ctr_redun				5	5	100.00
	otbn_sec_cm	328.000s	5371.118us	5	5	100.00

4/10 passed

40.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				4	10	40.00
	otbn_stress_all_with_rand_reset	385.000s	5085.763us	4	10	40.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	otbn_smoke_vectorized	26.000s	81.408us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				5 test runs
	otbn_stress_all_with_rand_reset	50625109888707143982426808541746450631154705440027226642180329750321465902787	183	UVM_INFO @ 862450988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	49580320037749026767531204046848535783927983046222146536013154663024368007631	476	UVM_INFO @ 6434180444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	111086944268816380180386098534616968025323813180536895821324063097705605024129	407	UVM_INFO @ 1336902888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	31944724644556843377869856557165378955855511474814915777695410266814469936979	254	UVM_INFO @ 435024894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	89724792801271591397106096097961801318288693565506765444020419477737099291560	282	UVM_INFO @ 5085763166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.				3 test runs
	otbn_passthru_mem_tl_intg_err	87561789918498782895852832657397558249011596561661244865901142573183015738254	91	UVM_INFO @ 11652232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_passthru_mem_tl_intg_err	100809093650623559567135694734655169605619964729171734086762960400866051354642	86	UVM_INFO @ 18855347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_passthru_mem_tl_intg_err	92331083382795564805055852483806891983448198788947478007304924113002391924397	96	UVM_INFO @ 237703988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error				2 test runs
	otbn_controller_ispr_rdata_err	66403330479333943656364559285535485493796482402689105889786200803678433343873	112	UVM_INFO @ 32781402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_escalate	96293098430398832530979695584270203119366888475661903761916182185100077037418	110	UVM_INFO @ 19345687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.				2 test runs
	otbn_multi	97661003833376781185698769756408653027450397945812341073154341982369156541623	160	UVM_INFO @ 185672696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_multi	103737355269057137248228988656757213211394973925313526840833544401860635839269	169	UVM_INFO @ 174748412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				2 test runs
	otbn_partial_wipe	16797208260841564006219911634361576046001778764386937895971124146062695967349	None	~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program) ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize assert bodysize is not None ^^^^^^^^^^^^^^^^^^^^ AssertionError ninja: build stopped: subcommand failed. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
	otbn_single	77435762730408313549981603287175490606368092967022615774925761035324429038388	None	~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program) ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize assert bodysize is not None ^^^^^^^^^^^^^^^^^^^^ AssertionError ninja: build stopped: subcommand failed. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
xmsim: E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_/otbn_idle_checker.sv,161): Assertion IdleIfLockedAndNotRotatingKeys_A has failed (* cycles, starting * PS)				1 test run
	otbn_partial_wipe	57576510637814959816152788346643289418004105575873841929624588694034385806674	116	UVM_ERROR @ 16342990 ps: (otbn_idle_checker.sv:161) [ASSERT FAILED] IdleIfLockedAndNotRotatingKeys_A UVM_INFO @ 16342990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)				1 test run
	otbn_stress_all_with_rand_reset	14389685356035907108336643574682197626358572538633033122242356253318151773316	287	UVM_INFO @ 2632966904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_/otbn_idle_checker.sv,171): Assertion NotRunningWhenLocked_A has failed				1 test run
	otbn_partial_wipe	82883118771011902879030332877276003124628182683891143400034033573637557454417	111	UVM_ERROR @ 7559264 ps: (otbn_idle_checker.sv:171) [ASSERT FAILED] NotRunningWhenLocked_A UVM_INFO @ 7559264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed				1 test run
	otbn_escalate	79607517353057044344744805629176717505054934229842751967065824019591910778417	115	UVM_ERROR @ 168769741 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A UVM_INFO @ 168769741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---